2 * Copyright (c) 2001 Matt Thomas.
3 * Copyright (c) 2001 Tsubai Masanari.
4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by
18 * Internet Research Institute, Inc.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (C) 2003 Benno Rice.
35 * All rights reserved.
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $
61 #include <sys/param.h>
62 #include <sys/systm.h>
66 #include <sys/kernel.h>
68 #include <sys/sysctl.h>
70 #include <machine/bus.h>
71 #include <machine/cpu.h>
72 #include <machine/hid.h>
73 #include <machine/md_var.h>
74 #include <machine/smp.h>
75 #include <machine/spr.h>
77 #include <dev/ofw/openfirm.h>
79 static void cpu_6xx_setup(int cpuid, uint16_t vers);
80 static void cpu_970_setup(int cpuid, uint16_t vers);
81 static void cpu_booke_setup(int cpuid, uint16_t vers);
83 int powerpc_pow_enabled;
84 void (*cpu_idle_hook)(sbintime_t) = NULL;
85 static void cpu_idle_60x(sbintime_t);
86 static void cpu_idle_booke(sbintime_t);
92 int features; /* Do not include PPC_FEATURE_32 or
93 * PPC_FEATURE_HAS_MMU */
94 void (*cpu_setup)(int cpuid, uint16_t vers);
96 #define REVFMT_MAJMIN 1 /* %u.%u */
97 #define REVFMT_HEX 2 /* 0x%04x */
98 #define REVFMT_DEC 3 /* %u */
99 static const struct cputab models[] = {
100 { "Motorola PowerPC 601", MPC601, REVFMT_DEC,
101 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, cpu_6xx_setup },
102 { "Motorola PowerPC 602", MPC602, REVFMT_DEC,
103 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
104 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN,
105 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
106 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN,
107 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
108 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN,
109 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
110 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN,
111 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
112 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN,
113 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
114 { "Motorola PowerPC 620", MPC620, REVFMT_HEX,
115 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
116 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN,
117 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
118 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN,
119 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
120 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN,
121 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
123 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN,
124 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
126 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN,
127 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
129 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN,
130 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
132 { "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN,
133 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
134 { "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN,
135 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
136 { "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN,
137 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
138 { "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN,
139 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, NULL },
140 { "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN,
141 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
143 { "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN,
144 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
146 { "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN,
147 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
149 { "IBM POWER8E", IBMPOWER8E, REVFMT_MAJMIN,
150 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
152 { "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN,
153 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
155 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN,
156 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
157 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN,
158 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
159 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN,
160 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
161 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN,
162 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
163 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN,
164 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
165 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN,
166 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
167 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN,
168 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
169 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN,
170 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
171 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN,
172 PPC_FEATURE_HAS_FPU, cpu_6xx_setup },
173 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN,
174 0, cpu_booke_setup },
175 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN,
176 0, cpu_booke_setup },
177 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN,
178 0, cpu_booke_setup },
179 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN,
180 0, cpu_booke_setup },
181 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN,
182 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU,
184 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, NULL },
187 static void cpu_6xx_print_cacheinfo(u_int, uint16_t);
188 static int cpu_feature_bit(SYSCTL_HANDLER_ARGS);
190 static char model[64];
191 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, "");
193 int cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU;
194 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLTYPE_INT | CTLFLAG_RD,
195 &cpu_features, sizeof(cpu_features), "IX", "PowerPC CPU features");
197 /* Provide some user-friendly aliases for bits in cpu_features */
198 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD,
199 0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I",
200 "Floating point instructions executed in hardware");
201 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD,
202 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec");
205 cpu_setup(u_int cpuid)
208 uint16_t vers, rev, revfmt;
210 const struct cputab *cp;
218 min = (pvr >> 0) & 0xff;
219 maj = min <= 4 ? 1 : 2;
225 maj = (pvr >> 4) & 0xf;
226 min = (pvr >> 0) & 0xf;
229 maj = (pvr >> 8) & 0xf;
230 min = (pvr >> 0) & 0xf;
233 for (cp = models; cp->version != 0; cp++) {
234 if (cp->version == vers)
240 if (rev == MPC750 && pvr == 15) {
241 name = "Motorola MPC755";
244 strncpy(model, name, sizeof(model) - 1);
246 printf("cpu%d: %s revision ", cpuid, name);
250 printf("%u.%u", maj, min);
253 printf("0x%04x", rev);
260 if (cpu_est_clockrate(0, &cps) == 0)
261 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100);
264 cpu_features |= cp->features;
265 printf("cpu%d: Features %b\n", cpuid, cpu_features,
266 PPC_FEATURE_BITMASK);
271 if (cp->cpu_setup != NULL)
272 cp->cpu_setup(cpuid, vers);
275 /* Get current clock frequency for the given cpu id. */
277 cpu_est_clockrate(int cpu_id, uint64_t *cps)
281 phandle_t cpu, dev, root;
285 vers = mfpvr() >> 16;
287 mtmsr(msr & ~PSL_EE);
299 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
301 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES));
303 *cps = (mfspr(SPR_PMC1) * 1000) + 4999;
304 mtspr(SPR_MMCR0, SPR_MMCR0_FC);
312 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
314 mtspr(SPR_970MMCR1, 0);
315 mtspr(SPR_970MMCRA, 0);
316 mtspr(SPR_970PMC1, 0);
318 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES));
322 mtspr(SPR_970MMCR0, SPR_MMCR0_FC);
323 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999;
333 dev = OF_child(root);
335 res = OF_getprop(dev, "name", buf, sizeof(buf));
336 if (res > 0 && strcmp(buf, "cpus") == 0)
342 res = OF_getprop(cpu, "device_type", buf,
344 if (res > 0 && strcmp(buf, "cpu") == 0)
350 if (OF_getprop(cpu, "ibm,extended-clock-frequency",
351 cps, sizeof(*cps)) >= 0) {
353 } else if (OF_getprop(cpu, "clock-frequency", cps,
354 sizeof(cell_t)) >= 0) {
364 cpu_6xx_setup(int cpuid, uint16_t vers)
366 register_t hid0, pvr;
369 hid0 = mfspr(SPR_HID0);
373 * Configure power-saving mode.
386 /* Select DOZE mode. */
387 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
388 hid0 |= HID0_DOZE | HID0_DPM;
389 powerpc_pow_enabled = 1;
397 /* Enable the 7450 branch caches */
398 hid0 |= HID0_SGE | HID0_BTIC;
399 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT;
400 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */
401 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200)
402 || (pvr >> 16) == MPC7457)
404 /* Select NAP mode. */
405 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
406 hid0 |= HID0_NAP | HID0_DPM;
407 powerpc_pow_enabled = 1;
411 /* No power-saving mode is available. */ ;
417 hid0 &= ~HID0_DBP; /* XXX correct? */
418 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
424 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
430 mtspr(SPR_HID0, hid0);
433 cpu_6xx_print_cacheinfo(cpuid, vers);
441 bitmask = HID0_7450_BITMASK;
444 bitmask = HID0_BITMASK;
448 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask);
450 if (cpu_idle_hook == NULL)
451 cpu_idle_hook = cpu_idle_60x;
456 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers)
460 hid = mfspr(SPR_HID0);
461 printf("cpu%u: ", cpuid);
462 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis");
463 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis");
465 printf("cpu%u: ", cpuid);
466 if (mfspr(SPR_L2CR) & L2CR_L2E) {
471 printf("256KB L2 cache, ");
472 if (mfspr(SPR_L3CR) & L3CR_L3E)
473 printf("%cMB L3 backside cache",
474 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1');
476 printf("L3 cache disabled");
480 printf("512KB L2 cache\n");
483 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {
494 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)
495 ? "through" : "back");
496 if (mfspr(SPR_L2CR) & L2CR_L2PE)
497 printf(", with parity");
498 printf(" backside cache\n");
502 printf("L2 cache disabled\n");
506 cpu_booke_setup(int cpuid, uint16_t vers)
511 hid0 = mfspr(SPR_HID0);
513 /* Programe power-management mode. */
514 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP);
517 mtspr(SPR_HID0, hid0);
519 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, HID0_E500_BITMASK);
522 if (cpu_idle_hook == NULL)
523 cpu_idle_hook = cpu_idle_booke;
527 cpu_970_setup(int cpuid, uint16_t vers)
530 uint32_t hid0_hi, hid0_lo;
532 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;"
533 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0));
535 /* Configure power-saving mode */
538 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM);
539 hid0_hi &= ~HID0_DOZE;
542 hid0_hi |= (HID0_NAP | HID0_DPM);
543 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP);
546 powerpc_pow_enabled = 1;
548 __asm __volatile (" \
550 sldi %0,%0,32; or %0,%0,%1; \
552 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
553 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \
555 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0));
557 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;"
558 : "=r" (hid0_hi) : "K" (SPR_HID0));
559 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK);
562 cpu_idle_hook = cpu_idle_60x;
566 cpu_feature_bit(SYSCTL_HANDLER_ARGS)
570 result = (cpu_features & arg2) ? 1 : 0;
572 return (sysctl_handle_int(oidp, &result, 0, req));
581 if ((mfmsr() & PSL_EE) != PSL_EE) {
582 struct thread *td = curthread;
583 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr);
584 panic("ints disabled in idleproc!");
588 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
591 if (cpu_idle_hook != NULL) {
594 sbt = cpu_idleclock();
603 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
608 cpu_idle_wakeup(int cpu)
614 cpu_idle_60x(sbintime_t sbt)
619 if (!powerpc_pow_enabled)
623 vers = mfpvr() >> 16;
636 dssall; sync; mtmsr %0; isync"
637 :: "r"(msr | PSL_POW));
641 mtmsr(msr | PSL_POW);
649 cpu_idle_booke(sbintime_t sbt)
656 /* Freescale E500 core RM section 6.4.1. */
657 __asm __volatile("msync; mtmsr %0; isync" ::