2 * Copyright (c) 1991 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Copyright (c) 2002 Benno Rice.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
58 * form: src/sys/i386/isa/intr_machdep.c,v 1.57 2001/07/20
65 #include <sys/param.h>
66 #include <sys/systm.h>
67 #include <sys/kernel.h>
68 #include <sys/queue.h>
70 #include <sys/cpuset.h>
71 #include <sys/interrupt.h>
74 #include <sys/malloc.h>
75 #include <sys/mutex.h>
78 #include <sys/syslog.h>
79 #include <sys/vmmeter.h>
82 #include <machine/frame.h>
83 #include <machine/intr_machdep.h>
84 #include <machine/md_var.h>
85 #include <machine/smp.h>
86 #include <machine/trap.h>
90 #define MAX_STRAY_LOG 5
92 static MALLOC_DEFINE(M_INTR, "intr", "interrupt handler data");
95 struct intr_event *event;
103 enum intr_trigger trig;
104 enum intr_polarity pol;
117 static u_int intrcnt_index = 0;
118 static struct mtx intr_table_lock;
119 static struct powerpc_intr *powerpc_intrs[INTR_VECTORS];
120 static struct pic piclist[MAX_PICS];
121 static u_int nvectors; /* Allocated vectors */
122 static u_int npics; /* PICs registered */
124 static u_int nirqs = 16; /* Allocated IRQS (ISA pre-allocated). */
126 static u_int nirqs = 0; /* Allocated IRQs. */
128 static u_int stray_count;
130 u_long intrcnt[INTR_VECTORS];
131 char intrnames[INTR_VECTORS * MAXCOMLEN];
132 size_t sintrcnt = sizeof(intrcnt);
133 size_t sintrnames = sizeof(intrnames);
138 static void *ipi_cookie;
142 intr_init(void *dummy __unused)
145 mtx_init(&intr_table_lock, "intr sources lock", NULL, MTX_DEF);
147 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
151 smp_intr_init(void *dummy __unused)
153 struct powerpc_intr *i;
156 for (vector = 0; vector < nvectors; vector++) {
157 i = powerpc_intrs[vector];
158 if (i != NULL && i->pic == root_pic)
159 PIC_BIND(i->pic, i->intline, i->cpu);
162 SYSINIT(smp_intr_init, SI_SUB_SMP, SI_ORDER_ANY, smp_intr_init, NULL);
166 intrcnt_setname(const char *name, int index)
169 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
174 intrcnt_add(const char *name, u_long **countp)
178 idx = atomic_fetchadd_int(&intrcnt_index, 1);
179 *countp = &intrcnt[idx];
180 intrcnt_setname(name, idx);
183 static struct powerpc_intr *
184 intr_lookup(u_int irq)
187 struct powerpc_intr *i, *iscan;
190 mtx_lock(&intr_table_lock);
191 for (vector = 0; vector < nvectors; vector++) {
192 i = powerpc_intrs[vector];
193 if (i != NULL && i->irq == irq) {
194 mtx_unlock(&intr_table_lock);
199 i = malloc(sizeof(*i), M_INTR, M_NOWAIT);
201 mtx_unlock(&intr_table_lock);
207 i->trig = INTR_TRIGGER_CONFORM;
208 i->pol = INTR_POLARITY_CONFORM;
218 CPU_SETOF(0, &i->cpu);
221 for (vector = 0; vector < INTR_VECTORS && vector <= nvectors;
223 iscan = powerpc_intrs[vector];
224 if (iscan != NULL && iscan->irq == irq)
226 if (iscan == NULL && i->vector == -1)
231 if (iscan == NULL && i->vector != -1) {
232 powerpc_intrs[i->vector] = i;
233 i->cntindex = atomic_fetchadd_int(&intrcnt_index, 1);
234 i->cntp = &intrcnt[i->cntindex];
235 sprintf(intrname, "irq%u:", i->irq);
236 intrcnt_setname(intrname, i->cntindex);
239 mtx_unlock(&intr_table_lock);
241 if (iscan != NULL || i->vector == -1) {
250 powerpc_map_irq(struct powerpc_intr *i)
256 for (idx = 0; idx < npics; idx++) {
258 cnt = p->irqs + p->ipis;
259 if (i->irq >= p->base && i->irq < p->base + cnt)
265 i->intline = i->irq - p->base;
268 /* Try a best guess if that failed */
276 powerpc_intr_eoi(void *arg)
278 struct powerpc_intr *i = arg;
280 PIC_EOI(i->pic, i->intline);
284 powerpc_intr_pre_ithread(void *arg)
286 struct powerpc_intr *i = arg;
288 PIC_MASK(i->pic, i->intline);
289 PIC_EOI(i->pic, i->intline);
293 powerpc_intr_post_ithread(void *arg)
295 struct powerpc_intr *i = arg;
297 PIC_UNMASK(i->pic, i->intline);
301 powerpc_assign_intr_cpu(void *arg, int cpu)
304 struct powerpc_intr *i = arg;
309 CPU_SETOF(cpu, &i->cpu);
311 if (!cold && i->pic != NULL && i->pic == root_pic)
312 PIC_BIND(i->pic, i->intline, i->cpu);
321 powerpc_register_pic(device_t dev, uint32_t node, u_int irqs, u_int ipis,
328 mtx_lock(&intr_table_lock);
330 /* XXX see powerpc_get_irq(). */
331 for (idx = 0; idx < npics; idx++) {
335 if (node != 0 || p->dev == dev)
346 p->base = (atpic) ? 0 : nirqs;
350 irq = p->base + irqs + ipis;
351 nirqs = MAX(nirqs, irq);
355 KASSERT(npics < MAX_PICS,
356 ("Number of PICs exceeds maximum (%d)", MAX_PICS));
358 mtx_unlock(&intr_table_lock);
362 powerpc_get_irq(uint32_t node, u_int pin)
369 mtx_lock(&intr_table_lock);
370 for (idx = 0; idx < npics; idx++) {
371 if (piclist[idx].node == node) {
372 mtx_unlock(&intr_table_lock);
373 return (piclist[idx].base + pin);
378 * XXX we should never encounter an unregistered PIC, but that
379 * can only be done when we properly support bus enumeration
380 * using multiple passes. Until then, fake an entry and give it
381 * some adhoc maximum number of IRQs and IPIs.
383 piclist[idx].dev = NULL;
384 piclist[idx].node = node;
385 piclist[idx].irqs = 124;
386 piclist[idx].ipis = 4;
387 piclist[idx].base = nirqs;
391 KASSERT(npics < MAX_PICS,
392 ("Number of PICs exceeds maximum (%d)", MAX_PICS));
394 mtx_unlock(&intr_table_lock);
396 return (piclist[idx].base + pin);
400 powerpc_enable_intr(void)
402 struct powerpc_intr *i;
409 panic("no PIC detected\n");
411 if (root_pic == NULL)
412 root_pic = piclist[0].dev;
415 /* Install an IPI handler. */
417 for (n = 0; n < npics; n++) {
418 if (piclist[n].dev != root_pic)
421 KASSERT(piclist[n].ipis != 0,
422 ("%s: SMP root PIC does not supply any IPIs",
424 error = powerpc_setup_intr("IPI",
425 MAP_IRQ(piclist[n].node, piclist[n].irqs),
426 powerpc_ipi_handler, NULL, NULL,
427 INTR_TYPE_MISC | INTR_EXCL, &ipi_cookie);
429 printf("unable to setup IPI handler\n");
434 * Some subterfuge: disable late EOI and mark this
435 * as an IPI to the dispatch layer.
437 i = intr_lookup(MAP_IRQ(piclist[n].node,
439 i->event->ie_post_filter = NULL;
445 for (vector = 0; vector < nvectors; vector++) {
446 i = powerpc_intrs[vector];
450 error = powerpc_map_irq(i);
454 if (i->trig == INTR_TRIGGER_INVALID)
455 PIC_TRANSLATE_CODE(i->pic, i->intline, i->fwcode,
457 if (i->trig != INTR_TRIGGER_CONFORM ||
458 i->pol != INTR_POLARITY_CONFORM)
459 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
461 if (i->event != NULL)
462 PIC_ENABLE(i->pic, i->intline, vector);
469 powerpc_setup_intr(const char *name, u_int irq, driver_filter_t filter,
470 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
472 struct powerpc_intr *i;
473 int error, enable = 0;
475 i = intr_lookup(irq);
479 if (i->event == NULL) {
480 error = intr_event_create(&i->event, (void *)i, 0, irq,
481 powerpc_intr_pre_ithread, powerpc_intr_post_ithread,
482 powerpc_intr_eoi, powerpc_assign_intr_cpu, "irq%u:", irq);
489 error = intr_event_add_handler(i->event, name, filter, handler, arg,
490 intr_priority(flags), flags, cookiep);
492 mtx_lock(&intr_table_lock);
493 intrcnt_setname(i->event->ie_fullname, i->cntindex);
494 mtx_unlock(&intr_table_lock);
497 error = powerpc_map_irq(i);
500 if (i->trig == INTR_TRIGGER_INVALID)
501 PIC_TRANSLATE_CODE(i->pic, i->intline,
502 i->fwcode, &i->trig, &i->pol);
504 if (i->trig != INTR_TRIGGER_CONFORM ||
505 i->pol != INTR_POLARITY_CONFORM)
506 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
508 if (i->pic == root_pic)
509 PIC_BIND(i->pic, i->intline, i->cpu);
512 PIC_ENABLE(i->pic, i->intline, i->vector);
519 powerpc_teardown_intr(void *cookie)
522 return (intr_event_remove_handler(cookie));
527 powerpc_bind_intr(u_int irq, u_char cpu)
529 struct powerpc_intr *i;
531 i = intr_lookup(irq);
535 return (intr_event_bind(i->event, cpu));
540 powerpc_fw_config_intr(int irq, int sense_code)
542 struct powerpc_intr *i;
544 i = intr_lookup(irq);
548 i->trig = INTR_TRIGGER_INVALID;
549 i->pol = INTR_POLARITY_CONFORM;
550 i->fwcode = sense_code;
552 if (!cold && i->pic != NULL) {
553 PIC_TRANSLATE_CODE(i->pic, i->intline, i->fwcode, &i->trig,
555 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
562 powerpc_config_intr(int irq, enum intr_trigger trig, enum intr_polarity pol)
564 struct powerpc_intr *i;
566 i = intr_lookup(irq);
573 if (!cold && i->pic != NULL)
574 PIC_CONFIG(i->pic, i->intline, trig, pol);
580 powerpc_dispatch_intr(u_int vector, struct trapframe *tf)
582 struct powerpc_intr *i;
583 struct intr_event *ie;
585 i = powerpc_intrs[vector];
592 KASSERT(ie != NULL, ("%s: interrupt without an event", __func__));
595 * IPIs are magical and need to be EOI'ed before filtering.
596 * This prevents races in IPI handling.
599 PIC_EOI(i->pic, i->intline);
601 if (intr_event_handle(ie, tf) != 0) {
608 if (stray_count <= MAX_STRAY_LOG) {
609 printf("stray irq %d\n", i ? i->irq : -1);
610 if (stray_count >= MAX_STRAY_LOG) {
611 printf("got %d stray interrupts, not logging anymore\n",
616 PIC_MASK(i->pic, i->intline);
620 powerpc_intr_mask(u_int irq)
622 struct powerpc_intr *i;
624 i = intr_lookup(irq);
625 if (i == NULL || i->pic == NULL)
628 PIC_MASK(i->pic, i->intline);
632 powerpc_intr_unmask(u_int irq)
634 struct powerpc_intr *i;
636 i = intr_lookup(irq);
637 if (i == NULL || i->pic == NULL)
640 PIC_UNMASK(i->pic, i->intline);