2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
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22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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35 * Copyright (c) 2002 Benno Rice.
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
60 * form: src/sys/i386/isa/intr_machdep.c,v 1.57 2001/07/20
67 #include <sys/param.h>
68 #include <sys/systm.h>
69 #include <sys/kernel.h>
70 #include <sys/queue.h>
72 #include <sys/cpuset.h>
73 #include <sys/interrupt.h>
76 #include <sys/malloc.h>
77 #include <sys/mutex.h>
80 #include <sys/syslog.h>
81 #include <sys/vmmeter.h>
84 #include <machine/frame.h>
85 #include <machine/intr_machdep.h>
86 #include <machine/md_var.h>
87 #include <machine/smp.h>
88 #include <machine/trap.h>
92 #define MAX_STRAY_LOG 5
94 static MALLOC_DEFINE(M_INTR, "intr", "interrupt handler data");
97 struct intr_event *event;
105 enum intr_trigger trig;
106 enum intr_polarity pol;
119 static u_int intrcnt_index = 0;
120 static struct mtx intr_table_lock;
121 static struct powerpc_intr *powerpc_intrs[INTR_VECTORS];
122 static struct pic piclist[MAX_PICS];
123 static u_int nvectors; /* Allocated vectors */
124 static u_int npics; /* PICs registered */
126 static u_int nirqs = 16; /* Allocated IRQS (ISA pre-allocated). */
128 static u_int nirqs = 0; /* Allocated IRQs. */
130 static u_int stray_count;
132 u_long intrcnt[INTR_VECTORS];
133 char intrnames[INTR_VECTORS * (MAXCOMLEN + 1)];
134 size_t sintrcnt = sizeof(intrcnt);
135 size_t sintrnames = sizeof(intrnames);
140 static void *ipi_cookie;
144 intr_init(void *dummy __unused)
147 mtx_init(&intr_table_lock, "intr sources lock", NULL, MTX_DEF);
149 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
153 smp_intr_init(void *dummy __unused)
155 struct powerpc_intr *i;
158 for (vector = 0; vector < nvectors; vector++) {
159 i = powerpc_intrs[vector];
160 if (i != NULL && i->event != NULL && i->pic == root_pic)
161 PIC_BIND(i->pic, i->intline, i->cpu);
164 SYSINIT(smp_intr_init, SI_SUB_SMP, SI_ORDER_ANY, smp_intr_init, NULL);
168 intrcnt_setname(const char *name, int index)
171 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
176 intrcnt_add(const char *name, u_long **countp)
180 idx = atomic_fetchadd_int(&intrcnt_index, 1);
181 KASSERT(idx < INTR_VECTORS, ("intrcnt_add: Interrupt counter index "
182 "reached INTR_VECTORS"));
183 *countp = &intrcnt[idx];
184 intrcnt_setname(name, idx);
187 static struct powerpc_intr *
188 intr_lookup(u_int irq)
191 struct powerpc_intr *i, *iscan;
194 mtx_lock(&intr_table_lock);
195 for (vector = 0; vector < nvectors; vector++) {
196 i = powerpc_intrs[vector];
197 if (i != NULL && i->irq == irq) {
198 mtx_unlock(&intr_table_lock);
203 i = malloc(sizeof(*i), M_INTR, M_NOWAIT);
205 mtx_unlock(&intr_table_lock);
211 i->trig = INTR_TRIGGER_CONFORM;
212 i->pol = INTR_POLARITY_CONFORM;
222 CPU_SETOF(0, &i->cpu);
225 for (vector = 0; vector < INTR_VECTORS && vector <= nvectors;
227 iscan = powerpc_intrs[vector];
228 if (iscan != NULL && iscan->irq == irq)
230 if (iscan == NULL && i->vector == -1)
235 if (iscan == NULL && i->vector != -1) {
236 powerpc_intrs[i->vector] = i;
237 i->cntindex = atomic_fetchadd_int(&intrcnt_index, 1);
238 i->cntp = &intrcnt[i->cntindex];
239 sprintf(intrname, "irq%u:", i->irq);
240 intrcnt_setname(intrname, i->cntindex);
243 mtx_unlock(&intr_table_lock);
245 if (iscan != NULL || i->vector == -1) {
254 powerpc_map_irq(struct powerpc_intr *i)
260 for (idx = 0; idx < npics; idx++) {
262 cnt = p->irqs + p->ipis;
263 if (i->irq >= p->base && i->irq < p->base + cnt)
269 i->intline = i->irq - p->base;
272 /* Try a best guess if that failed */
280 powerpc_intr_eoi(void *arg)
282 struct powerpc_intr *i = arg;
284 PIC_EOI(i->pic, i->intline);
288 powerpc_intr_pre_ithread(void *arg)
290 struct powerpc_intr *i = arg;
292 PIC_MASK(i->pic, i->intline);
293 PIC_EOI(i->pic, i->intline);
297 powerpc_intr_post_ithread(void *arg)
299 struct powerpc_intr *i = arg;
301 PIC_UNMASK(i->pic, i->intline);
305 powerpc_assign_intr_cpu(void *arg, int cpu)
308 struct powerpc_intr *i = arg;
313 CPU_SETOF(cpu, &i->cpu);
315 if (!cold && i->pic != NULL && i->pic == root_pic)
316 PIC_BIND(i->pic, i->intline, i->cpu);
325 powerpc_register_pic(device_t dev, uint32_t node, u_int irqs, u_int ipis,
332 mtx_lock(&intr_table_lock);
334 /* XXX see powerpc_get_irq(). */
335 for (idx = 0; idx < npics; idx++) {
339 if (node != 0 || p->dev == dev)
350 p->base = (atpic) ? 0 : nirqs;
354 irq = p->base + irqs + ipis;
355 nirqs = MAX(nirqs, irq);
359 KASSERT(npics < MAX_PICS,
360 ("Number of PICs exceeds maximum (%d)", MAX_PICS));
362 mtx_unlock(&intr_table_lock);
368 powerpc_get_irq(uint32_t node, u_int pin)
375 mtx_lock(&intr_table_lock);
376 for (idx = 0; idx < npics; idx++) {
377 if (piclist[idx].node == node) {
378 mtx_unlock(&intr_table_lock);
379 return (piclist[idx].base + pin);
384 * XXX we should never encounter an unregistered PIC, but that
385 * can only be done when we properly support bus enumeration
386 * using multiple passes. Until then, fake an entry and give it
387 * some adhoc maximum number of IRQs and IPIs.
389 piclist[idx].dev = NULL;
390 piclist[idx].node = node;
391 piclist[idx].irqs = 124;
392 piclist[idx].ipis = 4;
393 piclist[idx].base = nirqs;
397 KASSERT(npics < MAX_PICS,
398 ("Number of PICs exceeds maximum (%d)", MAX_PICS));
400 mtx_unlock(&intr_table_lock);
402 return (piclist[idx].base + pin);
406 powerpc_enable_intr(void)
408 struct powerpc_intr *i;
415 panic("no PIC detected\n");
417 if (root_pic == NULL)
418 root_pic = piclist[0].dev;
421 /* Install an IPI handler. */
423 for (n = 0; n < npics; n++) {
424 if (piclist[n].dev != root_pic)
427 KASSERT(piclist[n].ipis != 0,
428 ("%s: SMP root PIC does not supply any IPIs",
430 error = powerpc_setup_intr("IPI",
431 MAP_IRQ(piclist[n].node, piclist[n].irqs),
432 powerpc_ipi_handler, NULL, NULL,
433 INTR_TYPE_MISC | INTR_EXCL, &ipi_cookie);
435 printf("unable to setup IPI handler\n");
440 * Some subterfuge: disable late EOI and mark this
441 * as an IPI to the dispatch layer.
443 i = intr_lookup(MAP_IRQ(piclist[n].node,
445 i->event->ie_post_filter = NULL;
451 for (vector = 0; vector < nvectors; vector++) {
452 i = powerpc_intrs[vector];
456 error = powerpc_map_irq(i);
460 if (i->trig == INTR_TRIGGER_INVALID)
461 PIC_TRANSLATE_CODE(i->pic, i->intline, i->fwcode,
463 if (i->trig != INTR_TRIGGER_CONFORM ||
464 i->pol != INTR_POLARITY_CONFORM)
465 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
467 if (i->event != NULL)
468 PIC_ENABLE(i->pic, i->intline, vector);
475 powerpc_setup_intr(const char *name, u_int irq, driver_filter_t filter,
476 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
478 struct powerpc_intr *i;
479 int error, enable = 0;
481 i = intr_lookup(irq);
485 if (i->event == NULL) {
486 error = intr_event_create(&i->event, (void *)i, 0, irq,
487 powerpc_intr_pre_ithread, powerpc_intr_post_ithread,
488 powerpc_intr_eoi, powerpc_assign_intr_cpu, "irq%u:", irq);
495 error = intr_event_add_handler(i->event, name, filter, handler, arg,
496 intr_priority(flags), flags, cookiep);
498 mtx_lock(&intr_table_lock);
499 intrcnt_setname(i->event->ie_fullname, i->cntindex);
500 mtx_unlock(&intr_table_lock);
503 error = powerpc_map_irq(i);
506 if (i->trig == INTR_TRIGGER_INVALID)
507 PIC_TRANSLATE_CODE(i->pic, i->intline,
508 i->fwcode, &i->trig, &i->pol);
510 if (i->trig != INTR_TRIGGER_CONFORM ||
511 i->pol != INTR_POLARITY_CONFORM)
512 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
514 if (i->pic == root_pic)
515 PIC_BIND(i->pic, i->intline, i->cpu);
518 PIC_ENABLE(i->pic, i->intline, i->vector);
525 powerpc_teardown_intr(void *cookie)
528 return (intr_event_remove_handler(cookie));
533 powerpc_bind_intr(u_int irq, u_char cpu)
535 struct powerpc_intr *i;
537 i = intr_lookup(irq);
541 return (intr_event_bind(i->event, cpu));
546 powerpc_fw_config_intr(int irq, int sense_code)
548 struct powerpc_intr *i;
550 i = intr_lookup(irq);
554 i->trig = INTR_TRIGGER_INVALID;
555 i->pol = INTR_POLARITY_CONFORM;
556 i->fwcode = sense_code;
558 if (!cold && i->pic != NULL) {
559 PIC_TRANSLATE_CODE(i->pic, i->intline, i->fwcode, &i->trig,
561 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
568 powerpc_config_intr(int irq, enum intr_trigger trig, enum intr_polarity pol)
570 struct powerpc_intr *i;
572 i = intr_lookup(irq);
579 if (!cold && i->pic != NULL)
580 PIC_CONFIG(i->pic, i->intline, trig, pol);
586 powerpc_dispatch_intr(u_int vector, struct trapframe *tf)
588 struct powerpc_intr *i;
589 struct intr_event *ie;
591 i = powerpc_intrs[vector];
598 KASSERT(ie != NULL, ("%s: interrupt without an event", __func__));
601 * IPIs are magical and need to be EOI'ed before filtering.
602 * This prevents races in IPI handling.
605 PIC_EOI(i->pic, i->intline);
607 if (intr_event_handle(ie, tf) != 0) {
614 if (stray_count <= MAX_STRAY_LOG) {
615 printf("stray irq %d\n", i ? i->irq : -1);
616 if (stray_count >= MAX_STRAY_LOG) {
617 printf("got %d stray interrupts, not logging anymore\n",
622 PIC_MASK(i->pic, i->intline);
626 powerpc_intr_mask(u_int irq)
628 struct powerpc_intr *i;
630 i = intr_lookup(irq);
631 if (i == NULL || i->pic == NULL)
634 PIC_MASK(i->pic, i->intline);
638 powerpc_intr_unmask(u_int irq)
640 struct powerpc_intr *i;
642 i = intr_lookup(irq);
643 if (i == NULL || i->pic == NULL)
646 PIC_UNMASK(i->pic, i->intline);