2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
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17 * documentation and/or other materials provided with the distribution.
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22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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35 * Copyright (c) 2002 Benno Rice.
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
48 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
59 * from: @(#)isa.c 7.2 (Berkeley) 5/13/91
60 * form: src/sys/i386/isa/intr_machdep.c,v 1.57 2001/07/20
67 #include <sys/param.h>
68 #include <sys/systm.h>
69 #include <sys/kernel.h>
70 #include <sys/queue.h>
72 #include <sys/cpuset.h>
73 #include <sys/interrupt.h>
76 #include <sys/malloc.h>
77 #include <sys/mutex.h>
80 #include <sys/syslog.h>
81 #include <sys/vmmeter.h>
84 #include <machine/frame.h>
85 #include <machine/intr_machdep.h>
86 #include <machine/md_var.h>
87 #include <machine/smp.h>
88 #include <machine/trap.h>
92 #define MAX_STRAY_LOG 5
94 static MALLOC_DEFINE(M_INTR, "intr", "interrupt handler data");
97 struct intr_event *event;
105 enum intr_trigger trig;
106 enum intr_polarity pol;
119 static u_int intrcnt_index = 0;
120 static struct mtx intr_table_lock;
121 static struct powerpc_intr *powerpc_intrs[INTR_VECTORS];
122 static struct pic piclist[MAX_PICS];
123 static u_int nvectors; /* Allocated vectors */
124 static u_int npics; /* PICs registered */
126 static u_int nirqs = 16; /* Allocated IRQS (ISA pre-allocated). */
128 static u_int nirqs = 0; /* Allocated IRQs. */
130 static u_int stray_count;
132 u_long intrcnt[INTR_VECTORS];
133 char intrnames[INTR_VECTORS * MAXCOMLEN];
134 size_t sintrcnt = sizeof(intrcnt);
135 size_t sintrnames = sizeof(intrnames);
140 static void *ipi_cookie;
144 intr_init(void *dummy __unused)
147 mtx_init(&intr_table_lock, "intr sources lock", NULL, MTX_DEF);
149 SYSINIT(intr_init, SI_SUB_INTR, SI_ORDER_FIRST, intr_init, NULL);
153 smp_intr_init(void *dummy __unused)
155 struct powerpc_intr *i;
158 for (vector = 0; vector < nvectors; vector++) {
159 i = powerpc_intrs[vector];
160 if (i != NULL && i->pic == root_pic)
161 PIC_BIND(i->pic, i->intline, i->cpu);
164 SYSINIT(smp_intr_init, SI_SUB_SMP, SI_ORDER_ANY, smp_intr_init, NULL);
168 intrcnt_setname(const char *name, int index)
171 snprintf(intrnames + (MAXCOMLEN + 1) * index, MAXCOMLEN + 1, "%-*s",
176 intrcnt_add(const char *name, u_long **countp)
180 idx = atomic_fetchadd_int(&intrcnt_index, 1);
181 *countp = &intrcnt[idx];
182 intrcnt_setname(name, idx);
185 static struct powerpc_intr *
186 intr_lookup(u_int irq)
189 struct powerpc_intr *i, *iscan;
192 mtx_lock(&intr_table_lock);
193 for (vector = 0; vector < nvectors; vector++) {
194 i = powerpc_intrs[vector];
195 if (i != NULL && i->irq == irq) {
196 mtx_unlock(&intr_table_lock);
201 i = malloc(sizeof(*i), M_INTR, M_NOWAIT);
203 mtx_unlock(&intr_table_lock);
209 i->trig = INTR_TRIGGER_CONFORM;
210 i->pol = INTR_POLARITY_CONFORM;
220 CPU_SETOF(0, &i->cpu);
223 for (vector = 0; vector < INTR_VECTORS && vector <= nvectors;
225 iscan = powerpc_intrs[vector];
226 if (iscan != NULL && iscan->irq == irq)
228 if (iscan == NULL && i->vector == -1)
233 if (iscan == NULL && i->vector != -1) {
234 powerpc_intrs[i->vector] = i;
235 i->cntindex = atomic_fetchadd_int(&intrcnt_index, 1);
236 i->cntp = &intrcnt[i->cntindex];
237 sprintf(intrname, "irq%u:", i->irq);
238 intrcnt_setname(intrname, i->cntindex);
241 mtx_unlock(&intr_table_lock);
243 if (iscan != NULL || i->vector == -1) {
252 powerpc_map_irq(struct powerpc_intr *i)
258 for (idx = 0; idx < npics; idx++) {
260 cnt = p->irqs + p->ipis;
261 if (i->irq >= p->base && i->irq < p->base + cnt)
267 i->intline = i->irq - p->base;
270 /* Try a best guess if that failed */
278 powerpc_intr_eoi(void *arg)
280 struct powerpc_intr *i = arg;
282 PIC_EOI(i->pic, i->intline);
286 powerpc_intr_pre_ithread(void *arg)
288 struct powerpc_intr *i = arg;
290 PIC_MASK(i->pic, i->intline);
291 PIC_EOI(i->pic, i->intline);
295 powerpc_intr_post_ithread(void *arg)
297 struct powerpc_intr *i = arg;
299 PIC_UNMASK(i->pic, i->intline);
303 powerpc_assign_intr_cpu(void *arg, int cpu)
306 struct powerpc_intr *i = arg;
311 CPU_SETOF(cpu, &i->cpu);
313 if (!cold && i->pic != NULL && i->pic == root_pic)
314 PIC_BIND(i->pic, i->intline, i->cpu);
323 powerpc_register_pic(device_t dev, uint32_t node, u_int irqs, u_int ipis,
330 mtx_lock(&intr_table_lock);
332 /* XXX see powerpc_get_irq(). */
333 for (idx = 0; idx < npics; idx++) {
337 if (node != 0 || p->dev == dev)
348 p->base = (atpic) ? 0 : nirqs;
352 irq = p->base + irqs + ipis;
353 nirqs = MAX(nirqs, irq);
357 KASSERT(npics < MAX_PICS,
358 ("Number of PICs exceeds maximum (%d)", MAX_PICS));
360 mtx_unlock(&intr_table_lock);
364 powerpc_get_irq(uint32_t node, u_int pin)
371 mtx_lock(&intr_table_lock);
372 for (idx = 0; idx < npics; idx++) {
373 if (piclist[idx].node == node) {
374 mtx_unlock(&intr_table_lock);
375 return (piclist[idx].base + pin);
380 * XXX we should never encounter an unregistered PIC, but that
381 * can only be done when we properly support bus enumeration
382 * using multiple passes. Until then, fake an entry and give it
383 * some adhoc maximum number of IRQs and IPIs.
385 piclist[idx].dev = NULL;
386 piclist[idx].node = node;
387 piclist[idx].irqs = 124;
388 piclist[idx].ipis = 4;
389 piclist[idx].base = nirqs;
393 KASSERT(npics < MAX_PICS,
394 ("Number of PICs exceeds maximum (%d)", MAX_PICS));
396 mtx_unlock(&intr_table_lock);
398 return (piclist[idx].base + pin);
402 powerpc_enable_intr(void)
404 struct powerpc_intr *i;
411 panic("no PIC detected\n");
413 if (root_pic == NULL)
414 root_pic = piclist[0].dev;
417 /* Install an IPI handler. */
419 for (n = 0; n < npics; n++) {
420 if (piclist[n].dev != root_pic)
423 KASSERT(piclist[n].ipis != 0,
424 ("%s: SMP root PIC does not supply any IPIs",
426 error = powerpc_setup_intr("IPI",
427 MAP_IRQ(piclist[n].node, piclist[n].irqs),
428 powerpc_ipi_handler, NULL, NULL,
429 INTR_TYPE_MISC | INTR_EXCL, &ipi_cookie);
431 printf("unable to setup IPI handler\n");
436 * Some subterfuge: disable late EOI and mark this
437 * as an IPI to the dispatch layer.
439 i = intr_lookup(MAP_IRQ(piclist[n].node,
441 i->event->ie_post_filter = NULL;
447 for (vector = 0; vector < nvectors; vector++) {
448 i = powerpc_intrs[vector];
452 error = powerpc_map_irq(i);
456 if (i->trig == INTR_TRIGGER_INVALID)
457 PIC_TRANSLATE_CODE(i->pic, i->intline, i->fwcode,
459 if (i->trig != INTR_TRIGGER_CONFORM ||
460 i->pol != INTR_POLARITY_CONFORM)
461 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
463 if (i->event != NULL)
464 PIC_ENABLE(i->pic, i->intline, vector);
471 powerpc_setup_intr(const char *name, u_int irq, driver_filter_t filter,
472 driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep)
474 struct powerpc_intr *i;
475 int error, enable = 0;
477 i = intr_lookup(irq);
481 if (i->event == NULL) {
482 error = intr_event_create(&i->event, (void *)i, 0, irq,
483 powerpc_intr_pre_ithread, powerpc_intr_post_ithread,
484 powerpc_intr_eoi, powerpc_assign_intr_cpu, "irq%u:", irq);
491 error = intr_event_add_handler(i->event, name, filter, handler, arg,
492 intr_priority(flags), flags, cookiep);
494 mtx_lock(&intr_table_lock);
495 intrcnt_setname(i->event->ie_fullname, i->cntindex);
496 mtx_unlock(&intr_table_lock);
499 error = powerpc_map_irq(i);
502 if (i->trig == INTR_TRIGGER_INVALID)
503 PIC_TRANSLATE_CODE(i->pic, i->intline,
504 i->fwcode, &i->trig, &i->pol);
506 if (i->trig != INTR_TRIGGER_CONFORM ||
507 i->pol != INTR_POLARITY_CONFORM)
508 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
510 if (i->pic == root_pic)
511 PIC_BIND(i->pic, i->intline, i->cpu);
514 PIC_ENABLE(i->pic, i->intline, i->vector);
521 powerpc_teardown_intr(void *cookie)
524 return (intr_event_remove_handler(cookie));
529 powerpc_bind_intr(u_int irq, u_char cpu)
531 struct powerpc_intr *i;
533 i = intr_lookup(irq);
537 return (intr_event_bind(i->event, cpu));
542 powerpc_fw_config_intr(int irq, int sense_code)
544 struct powerpc_intr *i;
546 i = intr_lookup(irq);
550 i->trig = INTR_TRIGGER_INVALID;
551 i->pol = INTR_POLARITY_CONFORM;
552 i->fwcode = sense_code;
554 if (!cold && i->pic != NULL) {
555 PIC_TRANSLATE_CODE(i->pic, i->intline, i->fwcode, &i->trig,
557 PIC_CONFIG(i->pic, i->intline, i->trig, i->pol);
564 powerpc_config_intr(int irq, enum intr_trigger trig, enum intr_polarity pol)
566 struct powerpc_intr *i;
568 i = intr_lookup(irq);
575 if (!cold && i->pic != NULL)
576 PIC_CONFIG(i->pic, i->intline, trig, pol);
582 powerpc_dispatch_intr(u_int vector, struct trapframe *tf)
584 struct powerpc_intr *i;
585 struct intr_event *ie;
587 i = powerpc_intrs[vector];
594 KASSERT(ie != NULL, ("%s: interrupt without an event", __func__));
597 * IPIs are magical and need to be EOI'ed before filtering.
598 * This prevents races in IPI handling.
601 PIC_EOI(i->pic, i->intline);
603 if (intr_event_handle(ie, tf) != 0) {
610 if (stray_count <= MAX_STRAY_LOG) {
611 printf("stray irq %d\n", i ? i->irq : -1);
612 if (stray_count >= MAX_STRAY_LOG) {
613 printf("got %d stray interrupts, not logging anymore\n",
618 PIC_MASK(i->pic, i->intline);
622 powerpc_intr_mask(u_int irq)
624 struct powerpc_intr *i;
626 i = intr_lookup(irq);
627 if (i == NULL || i->pic == NULL)
630 PIC_MASK(i->pic, i->intline);
634 powerpc_intr_unmask(u_int irq)
636 struct powerpc_intr *i;
638 i = intr_lookup(irq);
639 if (i == NULL || i->pic == NULL)
642 PIC_UNMASK(i->pic, i->intline);