2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
38 * Copyright (C) 1995, 1996 TooLs GmbH.
39 * All rights reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by TooLs GmbH.
52 * 4. The name of TooLs GmbH may not be used to endorse or promote products
53 * derived from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
58 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
60 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
61 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
62 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
63 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
64 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
69 * Copyright (C) 2001 Benno Rice.
70 * All rights reserved.
72 * Redistribution and use in source and binary forms, with or without
73 * modification, are permitted provided that the following conditions
75 * 1. Redistributions of source code must retain the above copyright
76 * notice, this list of conditions and the following disclaimer.
77 * 2. Redistributions in binary form must reproduce the above copyright
78 * notice, this list of conditions and the following disclaimer in the
79 * documentation and/or other materials provided with the distribution.
81 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
82 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
83 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
84 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
85 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
86 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
87 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
88 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
89 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
90 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 #include <sys/cdefs.h>
94 __FBSDID("$FreeBSD$");
97 * Manages physical address maps.
99 * In addition to hardware address maps, this module is called upon to
100 * provide software-use-only maps which may or may not be stored in the
101 * same form as hardware maps. These pseudo-maps are used to store
102 * intermediate results from copy operations to and from address spaces.
104 * Since the information managed by this module is also stored by the
105 * logical address mapping module, this module may throw away valid virtual
106 * to physical mappings at almost any time. However, invalidations of
107 * mappings must be done as requested.
109 * In order to cope with hardware architectures which make virtual to
110 * physical map invalidates expensive, this module may delay invalidate
111 * reduced protection operations until such time as they are actually
112 * necessary. This module is given full information as to which processors
113 * are currently using which maps, and to when physical maps must be made
117 #include "opt_kstack_pages.h"
119 #include <sys/param.h>
120 #include <sys/kernel.h>
122 #include <sys/lock.h>
123 #include <sys/msgbuf.h>
124 #include <sys/mutex.h>
125 #include <sys/proc.h>
126 #include <sys/sysctl.h>
127 #include <sys/systm.h>
128 #include <sys/vmmeter.h>
130 #include <dev/ofw/openfirm.h>
133 #include <vm/vm_param.h>
134 #include <vm/vm_kern.h>
135 #include <vm/vm_page.h>
136 #include <vm/vm_map.h>
137 #include <vm/vm_object.h>
138 #include <vm/vm_extern.h>
139 #include <vm/vm_pageout.h>
140 #include <vm/vm_pager.h>
143 #include <machine/cpu.h>
144 #include <machine/powerpc.h>
145 #include <machine/bat.h>
146 #include <machine/frame.h>
147 #include <machine/md_var.h>
148 #include <machine/psl.h>
149 #include <machine/pte.h>
150 #include <machine/sr.h>
151 #include <machine/mmuvar.h>
157 #define TODO panic("%s: not implemented", __func__);
159 #define TLBIE(va) __asm __volatile("tlbie %0" :: "r"(va))
160 #define TLBSYNC() __asm __volatile("tlbsync");
161 #define SYNC() __asm __volatile("sync");
162 #define EIEIO() __asm __volatile("eieio");
164 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
165 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
166 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
168 #define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */
169 #define PVO_PTEGIDX_VALID 0x008 /* slot is valid */
170 #define PVO_WIRED 0x010 /* PVO entry is wired */
171 #define PVO_MANAGED 0x020 /* PVO entry is managed */
172 #define PVO_EXECUTABLE 0x040 /* PVO entry is executable */
173 #define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during
175 #define PVO_FAKE 0x100 /* fictitious phys page */
176 #define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF)
177 #define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE)
178 #define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE)
179 #define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
180 #define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
181 #define PVO_PTEGIDX_CLR(pvo) \
182 ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
183 #define PVO_PTEGIDX_SET(pvo, i) \
184 ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
186 #define MOEA_PVO_CHECK(pvo)
196 * Map of physical memory regions.
198 static struct mem_region *regions;
199 static struct mem_region *pregions;
200 u_int phys_avail_count;
201 int regions_sz, pregions_sz;
202 static struct ofw_map *translations;
204 extern struct pmap ofw_pmap;
209 * Lock for the pteg and pvo tables.
211 struct mtx moea_table_mutex;
216 static struct pteg *moea_pteg_table;
217 u_int moea_pteg_count;
218 u_int moea_pteg_mask;
223 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
224 struct pvo_head moea_pvo_kunmanaged =
225 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
226 struct pvo_head moea_pvo_unmanaged =
227 LIST_HEAD_INITIALIZER(moea_pvo_unmanaged); /* list of unmanaged pages */
229 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
230 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
232 #define BPVO_POOL_SIZE 32768
233 static struct pvo_entry *moea_bpvo_pool;
234 static int moea_bpvo_pool_index = 0;
236 #define VSID_NBPW (sizeof(u_int32_t) * 8)
237 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
239 static boolean_t moea_initialized = FALSE;
244 u_int moea_pte_valid = 0;
245 u_int moea_pte_overflow = 0;
246 u_int moea_pte_replacements = 0;
247 u_int moea_pvo_entries = 0;
248 u_int moea_pvo_enter_calls = 0;
249 u_int moea_pvo_remove_calls = 0;
250 u_int moea_pte_spills = 0;
251 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
253 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
254 &moea_pte_overflow, 0, "");
255 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
256 &moea_pte_replacements, 0, "");
257 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
259 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
260 &moea_pvo_enter_calls, 0, "");
261 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
262 &moea_pvo_remove_calls, 0, "");
263 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
264 &moea_pte_spills, 0, "");
266 struct pvo_entry *moea_pvo_zeropage;
267 struct mtx moea_pvo_zeropage_mtx;
269 vm_offset_t moea_rkva_start = VM_MIN_KERNEL_ADDRESS;
270 u_int moea_rkva_count = 4;
273 * Allocate physical memory for use in moea_bootstrap.
275 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
280 static int moea_pte_insert(u_int, struct pte *);
285 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
286 vm_offset_t, vm_offset_t, u_int, int);
287 static void moea_pvo_remove(struct pvo_entry *, int);
288 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
289 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
294 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
295 vm_prot_t, boolean_t);
296 static struct pvo_entry *moea_rkva_alloc(mmu_t);
297 static void moea_pa_map(struct pvo_entry *, vm_offset_t,
298 struct pte *, int *);
299 static void moea_pa_unmap(struct pvo_entry *, struct pte *, int *);
300 static void moea_syncicache(vm_offset_t, vm_size_t);
301 static boolean_t moea_query_bit(vm_page_t, int);
302 static u_int moea_clear_bit(vm_page_t, int, int *);
303 static void moea_kremove(mmu_t, vm_offset_t);
304 static void tlbia(void);
305 int moea_pte_spill(vm_offset_t);
308 * Kernel MMU interface
310 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
311 void moea_clear_modify(mmu_t, vm_page_t);
312 void moea_clear_reference(mmu_t, vm_page_t);
313 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
314 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
315 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
317 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
318 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
319 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
320 void moea_init(mmu_t);
321 boolean_t moea_is_modified(mmu_t, vm_page_t);
322 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
323 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
324 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
325 void moea_pinit(mmu_t, pmap_t);
326 void moea_pinit0(mmu_t, pmap_t);
327 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
328 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
329 void moea_qremove(mmu_t, vm_offset_t, int);
330 void moea_release(mmu_t, pmap_t);
331 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
332 void moea_remove_all(mmu_t, vm_page_t);
333 void moea_remove_write(mmu_t, vm_page_t);
334 void moea_zero_page(mmu_t, vm_page_t);
335 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
336 void moea_zero_page_idle(mmu_t, vm_page_t);
337 void moea_activate(mmu_t, struct thread *);
338 void moea_deactivate(mmu_t, struct thread *);
339 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
340 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
341 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
342 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
343 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
344 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
345 boolean_t moea_page_executable(mmu_t, vm_page_t);
347 static mmu_method_t moea_methods[] = {
348 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
349 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
350 MMUMETHOD(mmu_clear_reference, moea_clear_reference),
351 MMUMETHOD(mmu_copy_page, moea_copy_page),
352 MMUMETHOD(mmu_enter, moea_enter),
353 MMUMETHOD(mmu_enter_object, moea_enter_object),
354 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
355 MMUMETHOD(mmu_extract, moea_extract),
356 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
357 MMUMETHOD(mmu_init, moea_init),
358 MMUMETHOD(mmu_is_modified, moea_is_modified),
359 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
360 MMUMETHOD(mmu_map, moea_map),
361 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
362 MMUMETHOD(mmu_pinit, moea_pinit),
363 MMUMETHOD(mmu_pinit0, moea_pinit0),
364 MMUMETHOD(mmu_protect, moea_protect),
365 MMUMETHOD(mmu_qenter, moea_qenter),
366 MMUMETHOD(mmu_qremove, moea_qremove),
367 MMUMETHOD(mmu_release, moea_release),
368 MMUMETHOD(mmu_remove, moea_remove),
369 MMUMETHOD(mmu_remove_all, moea_remove_all),
370 MMUMETHOD(mmu_remove_write, moea_remove_write),
371 MMUMETHOD(mmu_zero_page, moea_zero_page),
372 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
373 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
374 MMUMETHOD(mmu_activate, moea_activate),
375 MMUMETHOD(mmu_deactivate, moea_deactivate),
377 /* Internal interfaces */
378 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
379 MMUMETHOD(mmu_mapdev, moea_mapdev),
380 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
381 MMUMETHOD(mmu_kextract, moea_kextract),
382 MMUMETHOD(mmu_kenter, moea_kenter),
383 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
384 MMUMETHOD(mmu_page_executable, moea_page_executable),
389 static mmu_def_t oea_mmu = {
398 va_to_sr(u_int *sr, vm_offset_t va)
400 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
403 static __inline u_int
404 va_to_pteg(u_int sr, vm_offset_t addr)
408 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
410 return (hash & moea_pteg_mask);
413 static __inline struct pvo_head *
414 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p)
418 pg = PHYS_TO_VM_PAGE(pa);
424 return (&moea_pvo_unmanaged);
426 return (&pg->md.mdpg_pvoh);
429 static __inline struct pvo_head *
430 vm_page_to_pvoh(vm_page_t m)
433 return (&m->md.mdpg_pvoh);
437 moea_attr_clear(vm_page_t m, int ptebit)
440 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
441 m->md.mdpg_attrs &= ~ptebit;
445 moea_attr_fetch(vm_page_t m)
448 return (m->md.mdpg_attrs);
452 moea_attr_save(vm_page_t m, int ptebit)
455 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
456 m->md.mdpg_attrs |= ptebit;
460 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
462 if (pt->pte_hi == pvo_pt->pte_hi)
469 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
471 return (pt->pte_hi & ~PTE_VALID) ==
472 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
473 ((va >> ADDR_API_SHFT) & PTE_API) | which);
477 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
480 mtx_assert(&moea_table_mutex, MA_OWNED);
483 * Construct a PTE. Default to IMB initially. Valid bit only gets
484 * set when the real pte is set in memory.
486 * Note: Don't set the valid bit for correct operation of tlb update.
488 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
489 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
494 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
497 mtx_assert(&moea_table_mutex, MA_OWNED);
498 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
502 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
505 mtx_assert(&moea_table_mutex, MA_OWNED);
508 * As shown in Section 7.6.3.2.3
510 pt->pte_lo &= ~ptebit;
518 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
521 mtx_assert(&moea_table_mutex, MA_OWNED);
522 pvo_pt->pte_hi |= PTE_VALID;
525 * Update the PTE as defined in section 7.6.3.1.
526 * Note that the REF/CHG bits are from pvo_pt and thus should havce
527 * been saved so this routine can restore them (if desired).
529 pt->pte_lo = pvo_pt->pte_lo;
531 pt->pte_hi = pvo_pt->pte_hi;
537 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
540 mtx_assert(&moea_table_mutex, MA_OWNED);
541 pvo_pt->pte_hi &= ~PTE_VALID;
544 * Force the reg & chg bits back into the PTEs.
549 * Invalidate the pte.
551 pt->pte_hi &= ~PTE_VALID;
560 * Save the reg & chg bits.
562 moea_pte_synch(pt, pvo_pt);
567 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
573 moea_pte_unset(pt, pvo_pt, va);
574 moea_pte_set(pt, pvo_pt);
578 * Quick sort callout for comparing memory regions.
580 static int mr_cmp(const void *a, const void *b);
581 static int om_cmp(const void *a, const void *b);
584 mr_cmp(const void *a, const void *b)
586 const struct mem_region *regiona;
587 const struct mem_region *regionb;
591 if (regiona->mr_start < regionb->mr_start)
593 else if (regiona->mr_start > regionb->mr_start)
600 om_cmp(const void *a, const void *b)
602 const struct ofw_map *mapa;
603 const struct ofw_map *mapb;
607 if (mapa->om_pa < mapb->om_pa)
609 else if (mapa->om_pa > mapb->om_pa)
616 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
619 phandle_t chosen, mmu;
623 vm_size_t size, physsz, hwphyssz;
624 vm_offset_t pa, va, off;
628 * Set up BAT0 to map the lowest 256 MB area
630 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
631 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
634 * Map PCI memory space.
636 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
637 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
639 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
640 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
642 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
643 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
645 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
646 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
651 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
652 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
655 * Use an IBAT and a DBAT to map the bottom segment of memory
658 batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
659 batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
660 __asm (".balign 32; \n"
661 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
662 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
663 :: "r"(batu), "r"(batl));
666 /* map frame buffer */
667 batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
668 batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
669 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
670 :: "r"(batu), "r"(batl));
675 batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
676 batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
677 __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
678 :: "r"(batu), "r"(batl));
682 * Set the start and end of kva.
684 virtual_avail = VM_MIN_KERNEL_ADDRESS;
685 virtual_end = VM_MAX_KERNEL_ADDRESS;
687 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
688 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
690 qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp);
691 for (i = 0; i < pregions_sz; i++) {
695 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
696 pregions[i].mr_start,
697 pregions[i].mr_start + pregions[i].mr_size,
698 pregions[i].mr_size);
700 * Install entries into the BAT table to allow all
701 * of physmem to be convered by on-demand BAT entries.
702 * The loop will sometimes set the same battable element
703 * twice, but that's fine since they won't be used for
706 pa = pregions[i].mr_start & 0xf0000000;
707 end = pregions[i].mr_start + pregions[i].mr_size;
709 u_int n = pa >> ADDR_SR_SHFT;
711 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
712 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
713 pa += SEGMENT_LENGTH;
717 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
718 panic("moea_bootstrap: phys_avail too small");
719 qsort(regions, regions_sz, sizeof(*regions), mr_cmp);
720 phys_avail_count = 0;
723 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
724 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
725 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
726 regions[i].mr_start + regions[i].mr_size,
729 (physsz + regions[i].mr_size) >= hwphyssz) {
730 if (physsz < hwphyssz) {
731 phys_avail[j] = regions[i].mr_start;
732 phys_avail[j + 1] = regions[i].mr_start +
739 phys_avail[j] = regions[i].mr_start;
740 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
742 physsz += regions[i].mr_size;
744 physmem = btoc(physsz);
747 * Allocate PTEG table.
750 moea_pteg_count = PTEGCOUNT;
752 moea_pteg_count = 0x1000;
754 while (moea_pteg_count < physmem)
755 moea_pteg_count <<= 1;
757 moea_pteg_count >>= 1;
758 #endif /* PTEGCOUNT */
760 size = moea_pteg_count * sizeof(struct pteg);
761 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
763 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
764 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
765 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
766 moea_pteg_mask = moea_pteg_count - 1;
769 * Allocate pv/overflow lists.
771 size = sizeof(struct pvo_head) * moea_pteg_count;
772 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
774 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
775 for (i = 0; i < moea_pteg_count; i++)
776 LIST_INIT(&moea_pvo_table[i]);
779 * Initialize the lock that synchronizes access to the pteg and pvo
782 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
786 * Allocate the message buffer.
788 msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, 0);
791 * Initialise the unmanaged pvo pool.
793 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
794 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
795 moea_bpvo_pool_index = 0;
798 * Make sure kernel vsid is allocated as well as VSID 0.
800 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
801 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
802 moea_vsid_bitmap[0] |= 1;
805 * Set up the Open Firmware pmap and add it's mappings.
807 moea_pinit(mmup, &ofw_pmap);
808 ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
809 ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
810 if ((chosen = OF_finddevice("/chosen")) == -1)
811 panic("moea_bootstrap: can't find /chosen");
812 OF_getprop(chosen, "mmu", &mmui, 4);
813 if ((mmu = OF_instance_to_package(mmui)) == -1)
814 panic("moea_bootstrap: can't get mmu package");
815 if ((sz = OF_getproplen(mmu, "translations")) == -1)
816 panic("moea_bootstrap: can't get ofw translation count");
818 for (i = 0; phys_avail[i] != 0; i += 2) {
819 if (phys_avail[i + 1] >= sz) {
820 translations = (struct ofw_map *)phys_avail[i];
824 if (translations == NULL)
825 panic("moea_bootstrap: no space to copy translations");
826 bzero(translations, sz);
827 if (OF_getprop(mmu, "translations", translations, sz) == -1)
828 panic("moea_bootstrap: can't get ofw translations");
829 CTR0(KTR_PMAP, "moea_bootstrap: translations");
830 sz /= sizeof(*translations);
831 qsort(translations, sz, sizeof (*translations), om_cmp);
832 for (i = 0, ofw_mappings = 0; i < sz; i++) {
833 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
834 translations[i].om_pa, translations[i].om_va,
835 translations[i].om_len);
838 * If the mapping is 1:1, let the RAM and device on-demand
839 * BAT tables take care of the translation.
841 if (translations[i].om_va == translations[i].om_pa)
844 /* Enter the pages */
845 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
848 m.phys_addr = translations[i].om_pa + off;
849 PMAP_LOCK(&ofw_pmap);
850 moea_enter_locked(&ofw_pmap,
851 translations[i].om_va + off, &m,
853 PMAP_UNLOCK(&ofw_pmap);
862 * Initialize the kernel pmap (which is statically allocated).
864 PMAP_LOCK_INIT(kernel_pmap);
865 for (i = 0; i < 16; i++) {
866 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
868 kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
869 kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
870 kernel_pmap->pm_active = ~0;
873 * Allocate a kernel stack with a guard page for thread0 and map it
874 * into the kernel page map.
876 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0);
878 kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE);
879 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", kstack0_phys,
881 virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE;
882 for (i = 0; i < KSTACK_PAGES; i++) {
883 pa = kstack0_phys + i * PAGE_SIZE;
884 va = kstack0 + i * PAGE_SIZE;
885 moea_kenter(mmup, va, pa);
890 * Calculate the last available physical address.
892 for (i = 0; phys_avail[i + 2] != 0; i += 2)
894 Maxmem = powerpc_btop(phys_avail[i + 1]);
897 * Allocate virtual address space for the message buffer.
899 msgbufp = (struct msgbuf *)virtual_avail;
900 virtual_avail += round_page(MSGBUF_SIZE);
903 * Initialize hardware.
905 for (i = 0; i < 16; i++) {
906 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
908 __asm __volatile ("mtsr %0,%1"
909 :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
910 __asm __volatile ("mtsr %0,%1"
911 :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
912 __asm __volatile ("sync; mtsdr1 %0; isync"
913 :: "r"((u_int)moea_pteg_table | (moea_pteg_mask >> 10)));
920 * Activate a user pmap. The pmap must be activated before it's address
921 * space can be accessed in any way.
924 moea_activate(mmu_t mmu, struct thread *td)
929 * Load all the data we need up front to encourage the compiler to
930 * not issue any loads while we have interrupts disabled below.
932 pm = &td->td_proc->p_vmspace->vm_pmap;
934 if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL)
937 pm->pm_active |= PCPU_GET(cpumask);
938 PCPU_SET(curpmap, pmr);
942 moea_deactivate(mmu_t mmu, struct thread *td)
946 pm = &td->td_proc->p_vmspace->vm_pmap;
947 pm->pm_active &= ~(PCPU_GET(cpumask));
948 PCPU_SET(curpmap, NULL);
952 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
954 struct pvo_entry *pvo;
957 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
961 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
962 pm->pm_stats.wired_count++;
963 pvo->pvo_vaddr |= PVO_WIRED;
965 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
966 pm->pm_stats.wired_count--;
967 pvo->pvo_vaddr &= ~PVO_WIRED;
974 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
979 dst = VM_PAGE_TO_PHYS(mdst);
980 src = VM_PAGE_TO_PHYS(msrc);
982 kcopy((void *)src, (void *)dst, PAGE_SIZE);
986 * Zero a page of physical memory by temporarily mapping it into the tlb.
989 moea_zero_page(mmu_t mmu, vm_page_t m)
991 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
994 if (pa < SEGMENT_LENGTH) {
996 } else if (moea_initialized) {
997 if (moea_pvo_zeropage == NULL) {
998 moea_pvo_zeropage = moea_rkva_alloc(mmu);
999 mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
1002 mtx_lock(&moea_pvo_zeropage_mtx);
1003 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
1004 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
1006 panic("moea_zero_page: can't zero pa %#x", pa);
1009 bzero(va, PAGE_SIZE);
1011 if (pa >= SEGMENT_LENGTH) {
1012 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
1013 mtx_unlock(&moea_pvo_zeropage_mtx);
1018 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1020 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1023 if (pa < SEGMENT_LENGTH) {
1025 } else if (moea_initialized) {
1026 if (moea_pvo_zeropage == NULL) {
1027 moea_pvo_zeropage = moea_rkva_alloc(mmu);
1028 mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
1031 mtx_lock(&moea_pvo_zeropage_mtx);
1032 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
1033 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
1035 panic("moea_zero_page: can't zero pa %#x", pa);
1038 bzero(va + off, size);
1040 if (pa >= SEGMENT_LENGTH) {
1041 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
1042 mtx_unlock(&moea_pvo_zeropage_mtx);
1047 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1050 moea_zero_page(mmu, m);
1054 * Map the given physical page at the specified virtual address in the
1055 * target pmap with the protection requested. If specified the page
1056 * will be wired down.
1059 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1063 vm_page_lock_queues();
1065 moea_enter_locked(pmap, va, m, prot, wired);
1066 vm_page_unlock_queues();
1071 * Map the given physical page at the specified virtual address in the
1072 * target pmap with the protection requested. If specified the page
1073 * will be wired down.
1075 * The page queues and pmap must be locked.
1078 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1081 struct pvo_head *pvo_head;
1084 u_int pte_lo, pvo_flags, was_exec, i;
1087 if (!moea_initialized) {
1088 pvo_head = &moea_pvo_kunmanaged;
1089 zone = moea_upvo_zone;
1092 was_exec = PTE_EXEC;
1094 pvo_head = vm_page_to_pvoh(m);
1096 zone = moea_mpvo_zone;
1097 pvo_flags = PVO_MANAGED;
1100 if (pmap_bootstrapped)
1101 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1102 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1104 /* XXX change the pvo head for fake pages */
1105 if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) {
1106 pvo_flags &= ~PVO_MANAGED;
1107 pvo_head = &moea_pvo_kunmanaged;
1108 zone = moea_upvo_zone;
1112 * If this is a managed page, and it's the first reference to the page,
1113 * clear the execness of the page. Otherwise fetch the execness.
1115 if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) {
1116 if (LIST_EMPTY(pvo_head)) {
1117 moea_attr_clear(pg, PTE_EXEC);
1119 was_exec = moea_attr_fetch(pg) & PTE_EXEC;
1124 * Assume the page is cache inhibited and access is guarded unless
1125 * it's in our available memory array.
1127 pte_lo = PTE_I | PTE_G;
1128 for (i = 0; i < pregions_sz; i++) {
1129 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) &&
1130 (VM_PAGE_TO_PHYS(m) <
1131 (pregions[i].mr_start + pregions[i].mr_size))) {
1132 pte_lo &= ~(PTE_I | PTE_G);
1137 if (prot & VM_PROT_WRITE) {
1139 if (pmap_bootstrapped)
1140 vm_page_flag_set(m, PG_WRITEABLE);
1144 if (prot & VM_PROT_EXECUTE)
1145 pvo_flags |= PVO_EXECUTABLE;
1148 pvo_flags |= PVO_WIRED;
1150 if ((m->flags & PG_FICTITIOUS) != 0)
1151 pvo_flags |= PVO_FAKE;
1153 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1157 * Flush the real page from the instruction cache if this page is
1158 * mapped executable and cacheable and was not previously mapped (or
1159 * was not mapped executable).
1161 if (error == 0 && (pvo_flags & PVO_EXECUTABLE) &&
1162 (pte_lo & PTE_I) == 0 && was_exec == 0) {
1164 * Flush the real memory from the cache.
1166 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1168 moea_attr_save(pg, PTE_EXEC);
1171 /* XXX syncicache always until problems are sorted */
1172 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1176 * Maps a sequence of resident pages belonging to the same object.
1177 * The sequence begins with the given page m_start. This page is
1178 * mapped at the given virtual address start. Each subsequent page is
1179 * mapped at a virtual address that is offset from start by the same
1180 * amount as the page is offset from m_start within the object. The
1181 * last page in the sequence is the page with the largest offset from
1182 * m_start that can be mapped at a virtual address less than the given
1183 * virtual address end. Not every virtual page between start and end
1184 * is mapped; only those for which a resident page exists with the
1185 * corresponding offset from m_start are mapped.
1188 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1189 vm_page_t m_start, vm_prot_t prot)
1192 vm_pindex_t diff, psize;
1194 psize = atop(end - start);
1197 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1198 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1199 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1200 m = TAILQ_NEXT(m, listq);
1206 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1211 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1218 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1220 struct pvo_entry *pvo;
1224 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1228 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1234 * Atomically extract and hold the physical page with the given
1235 * pmap and virtual address pair if that mapping permits the given
1239 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1241 struct pvo_entry *pvo;
1245 vm_page_lock_queues();
1247 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1248 if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) &&
1249 ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW ||
1250 (prot & VM_PROT_WRITE) == 0)) {
1251 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
1254 vm_page_unlock_queues();
1260 moea_init(mmu_t mmu)
1263 CTR0(KTR_PMAP, "moea_init");
1265 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1266 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1267 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1268 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1269 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1270 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1271 moea_initialized = TRUE;
1275 moea_is_modified(mmu_t mmu, vm_page_t m)
1278 if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0)
1281 return (moea_query_bit(m, PTE_CHG));
1285 moea_clear_reference(mmu_t mmu, vm_page_t m)
1288 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1290 moea_clear_bit(m, PTE_REF, NULL);
1294 moea_clear_modify(mmu_t mmu, vm_page_t m)
1297 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1299 moea_clear_bit(m, PTE_CHG, NULL);
1303 * Clear the write and modified bits in each of the given page's mappings.
1306 moea_remove_write(mmu_t mmu, vm_page_t m)
1308 struct pvo_entry *pvo;
1313 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1314 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
1315 (m->flags & PG_WRITEABLE) == 0)
1317 lo = moea_attr_fetch(m);
1319 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1320 pmap = pvo->pvo_pmap;
1322 if ((pvo->pvo_pte.pte_lo & PTE_PP) != PTE_BR) {
1323 pt = moea_pvo_to_pte(pvo, -1);
1324 pvo->pvo_pte.pte_lo &= ~PTE_PP;
1325 pvo->pvo_pte.pte_lo |= PTE_BR;
1327 moea_pte_synch(pt, &pvo->pvo_pte);
1328 lo |= pvo->pvo_pte.pte_lo;
1329 pvo->pvo_pte.pte_lo &= ~PTE_CHG;
1330 moea_pte_change(pt, &pvo->pvo_pte,
1332 mtx_unlock(&moea_table_mutex);
1337 if ((lo & PTE_CHG) != 0) {
1338 moea_attr_clear(m, PTE_CHG);
1341 vm_page_flag_clear(m, PG_WRITEABLE);
1345 * moea_ts_referenced:
1347 * Return a count of reference bits for a page, clearing those bits.
1348 * It is not necessary for every reference bit to be cleared, but it
1349 * is necessary that 0 only be returned when there are truly no
1350 * reference bits set.
1352 * XXX: The exact number of bits to check and clear is a matter that
1353 * should be tested and standardized at some point in the future for
1354 * optimal aging of shared pages.
1357 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1361 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
1364 count = moea_clear_bit(m, PTE_REF, NULL);
1370 * Map a wired page into kernel virtual address space.
1373 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
1380 if (va < VM_MIN_KERNEL_ADDRESS)
1381 panic("moea_kenter: attempt to enter non-kernel address %#x",
1385 pte_lo = PTE_I | PTE_G;
1386 for (i = 0; i < pregions_sz; i++) {
1387 if ((pa >= pregions[i].mr_start) &&
1388 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
1389 pte_lo &= ~(PTE_I | PTE_G);
1394 PMAP_LOCK(kernel_pmap);
1395 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1396 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1398 if (error != 0 && error != ENOENT)
1399 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1403 * Flush the real memory from the instruction cache.
1405 if ((pte_lo & (PTE_I | PTE_G)) == 0) {
1406 moea_syncicache(pa, PAGE_SIZE);
1408 PMAP_UNLOCK(kernel_pmap);
1412 * Extract the physical page address associated with the given kernel virtual
1416 moea_kextract(mmu_t mmu, vm_offset_t va)
1418 struct pvo_entry *pvo;
1421 #ifdef UMA_MD_SMALL_ALLOC
1423 * Allow direct mappings
1425 if (va < VM_MIN_KERNEL_ADDRESS) {
1430 PMAP_LOCK(kernel_pmap);
1431 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1432 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1433 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1434 PMAP_UNLOCK(kernel_pmap);
1439 * Remove a wired page from kernel virtual address space.
1442 moea_kremove(mmu_t mmu, vm_offset_t va)
1445 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1449 * Map a range of physical addresses into kernel virtual address space.
1451 * The value passed in *virt is a suggested virtual address for the mapping.
1452 * Architectures which can support a direct-mapped physical to virtual region
1453 * can return the appropriate address within that region, leaving '*virt'
1454 * unchanged. We cannot and therefore do not; *virt is updated with the
1455 * first usable address after the mapped region.
1458 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
1459 vm_offset_t pa_end, int prot)
1461 vm_offset_t sva, va;
1465 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1466 moea_kenter(mmu, va, pa_start);
1472 * Returns true if the pmap's pv is one of the first
1473 * 16 pvs linked to from this page. This count may
1474 * be changed upwards or downwards in the future; it
1475 * is only necessary that true be returned for a small
1476 * subset of pmaps for proper page aging.
1479 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1482 struct pvo_entry *pvo;
1484 if (!moea_initialized || (m->flags & PG_FICTITIOUS))
1488 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1489 if (pvo->pvo_pmap == pmap)
1498 static u_int moea_vsidcontext;
1501 moea_pinit(mmu_t mmu, pmap_t pmap)
1506 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1507 PMAP_LOCK_INIT(pmap);
1510 __asm __volatile("mftb %0" : "=r"(entropy));
1513 * Allocate some segment registers for this pmap.
1515 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1519 * Create a new value by mutiplying by a prime and adding in
1520 * entropy from the timebase register. This is to make the
1521 * VSID more random so that the PT hash function collides
1522 * less often. (Note that the prime casues gcc to do shifts
1523 * instead of a multiply.)
1525 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1526 hash = moea_vsidcontext & (NPMAPS - 1);
1527 if (hash == 0) /* 0 is special, avoid it */
1530 mask = 1 << (hash & (VSID_NBPW - 1));
1531 hash = (moea_vsidcontext & 0xfffff);
1532 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1533 /* anything free in this bucket? */
1534 if (moea_vsid_bitmap[n] == 0xffffffff) {
1535 entropy = (moea_vsidcontext >> 20);
1538 i = ffs(~moea_vsid_bitmap[i]) - 1;
1540 hash &= 0xfffff & ~(VSID_NBPW - 1);
1543 moea_vsid_bitmap[n] |= mask;
1544 for (i = 0; i < 16; i++)
1545 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1549 panic("moea_pinit: out of segments");
1553 * Initialize the pmap associated with process 0.
1556 moea_pinit0(mmu_t mmu, pmap_t pm)
1559 moea_pinit(mmu, pm);
1560 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1564 * Set the physical protection on the specified range of this map as requested.
1567 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1570 struct pvo_entry *pvo;
1574 CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva,
1578 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1579 ("moea_protect: non current pmap"));
1581 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1582 moea_remove(mmu, pm, sva, eva);
1586 vm_page_lock_queues();
1588 for (; sva < eva; sva += PAGE_SIZE) {
1589 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1593 if ((prot & VM_PROT_EXECUTE) == 0)
1594 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1597 * Grab the PTE pointer before we diddle with the cached PTE
1600 pt = moea_pvo_to_pte(pvo, pteidx);
1602 * Change the protection of the page.
1604 pvo->pvo_pte.pte_lo &= ~PTE_PP;
1605 pvo->pvo_pte.pte_lo |= PTE_BR;
1608 * If the PVO is in the page table, update that pte as well.
1611 moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1612 mtx_unlock(&moea_table_mutex);
1615 vm_page_unlock_queues();
1620 * Map a list of wired pages into kernel virtual address space. This is
1621 * intended for temporary mappings which do not need page modification or
1622 * references recorded. Existing mappings in the region are overwritten.
1625 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1630 while (count-- > 0) {
1631 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1638 * Remove page mappings from kernel virtual address space. Intended for
1639 * temporary mappings entered by moea_qenter.
1642 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1647 while (count-- > 0) {
1648 moea_kremove(mmu, va);
1654 moea_release(mmu_t mmu, pmap_t pmap)
1659 * Free segment register's VSID
1661 if (pmap->pm_sr[0] == 0)
1662 panic("moea_release");
1664 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1665 mask = 1 << (idx % VSID_NBPW);
1667 moea_vsid_bitmap[idx] &= ~mask;
1668 PMAP_LOCK_DESTROY(pmap);
1672 * Remove the given range of addresses from the specified map.
1675 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1677 struct pvo_entry *pvo;
1680 vm_page_lock_queues();
1682 for (; sva < eva; sva += PAGE_SIZE) {
1683 pvo = moea_pvo_find_va(pm, sva, &pteidx);
1685 moea_pvo_remove(pvo, pteidx);
1689 vm_page_unlock_queues();
1693 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1694 * will reflect changes in pte's back to the vm_page.
1697 moea_remove_all(mmu_t mmu, vm_page_t m)
1699 struct pvo_head *pvo_head;
1700 struct pvo_entry *pvo, *next_pvo;
1703 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1705 pvo_head = vm_page_to_pvoh(m);
1706 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1707 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1709 MOEA_PVO_CHECK(pvo); /* sanity check */
1710 pmap = pvo->pvo_pmap;
1712 moea_pvo_remove(pvo, -1);
1715 vm_page_flag_clear(m, PG_WRITEABLE);
1719 * Allocate a physical page of memory directly from the phys_avail map.
1720 * Can only be called from moea_bootstrap before avail start and end are
1724 moea_bootstrap_alloc(vm_size_t size, u_int align)
1729 size = round_page(size);
1730 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1732 s = (phys_avail[i] + align - 1) & ~(align - 1);
1737 if (s < phys_avail[i] || e > phys_avail[i + 1])
1740 if (s == phys_avail[i]) {
1741 phys_avail[i] += size;
1742 } else if (e == phys_avail[i + 1]) {
1743 phys_avail[i + 1] -= size;
1745 for (j = phys_avail_count * 2; j > i; j -= 2) {
1746 phys_avail[j] = phys_avail[j - 2];
1747 phys_avail[j + 1] = phys_avail[j - 1];
1750 phys_avail[i + 3] = phys_avail[i + 1];
1751 phys_avail[i + 1] = s;
1752 phys_avail[i + 2] = e;
1758 panic("moea_bootstrap_alloc: could not allocate memory");
1762 * Return an unmapped pvo for a kernel virtual address.
1763 * Used by pmap functions that operate on physical pages.
1765 static struct pvo_entry *
1766 moea_rkva_alloc(mmu_t mmu)
1768 struct pvo_entry *pvo;
1773 if (moea_rkva_count == 0)
1774 panic("moea_rkva_alloc: no more reserved KVAs");
1776 kva = moea_rkva_start + (PAGE_SIZE * --moea_rkva_count);
1777 moea_kenter(mmu, kva, 0);
1779 pvo = moea_pvo_find_va(kernel_pmap, kva, &pteidx);
1782 panic("moea_kva_alloc: moea_pvo_find_va failed");
1784 pt = moea_pvo_to_pte(pvo, pteidx);
1787 panic("moea_kva_alloc: moea_pvo_to_pte failed");
1789 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1790 mtx_unlock(&moea_table_mutex);
1791 PVO_PTEGIDX_CLR(pvo);
1793 moea_pte_overflow++;
1799 moea_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt,
1805 * If this pvo already has a valid pte, we need to save it so it can
1806 * be restored later. We then just reload the new PTE over the old
1809 if (saved_pt != NULL) {
1810 pt = moea_pvo_to_pte(pvo, -1);
1813 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1814 mtx_unlock(&moea_table_mutex);
1815 PVO_PTEGIDX_CLR(pvo);
1816 moea_pte_overflow++;
1819 *saved_pt = pvo->pvo_pte;
1821 pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
1824 pvo->pvo_pte.pte_lo |= pa;
1826 if (!moea_pte_spill(pvo->pvo_vaddr))
1827 panic("moea_pa_map: could not spill pvo %p", pvo);
1829 if (depth_p != NULL)
1834 moea_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p)
1838 pt = moea_pvo_to_pte(pvo, -1);
1841 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
1842 mtx_unlock(&moea_table_mutex);
1843 PVO_PTEGIDX_CLR(pvo);
1844 moea_pte_overflow++;
1847 pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
1850 * If there is a saved PTE and it's valid, restore it and return.
1852 if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) {
1853 if (depth_p != NULL && --(*depth_p) == 0)
1854 panic("moea_pa_unmap: restoring but depth == 0");
1856 pvo->pvo_pte = *saved_pt;
1858 if (!moea_pte_spill(pvo->pvo_vaddr))
1859 panic("moea_pa_unmap: could not spill pvo %p", pvo);
1864 moea_syncicache(vm_offset_t pa, vm_size_t len)
1866 __syncicache((void *)pa, len);
1875 for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) {
1884 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1885 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1887 struct pvo_entry *pvo;
1894 moea_pvo_enter_calls++;
1899 * Compute the PTE Group index.
1902 sr = va_to_sr(pm->pm_sr, va);
1903 ptegidx = va_to_pteg(sr, va);
1906 * Remove any existing mapping for this page. Reuse the pvo entry if
1907 * there is a mapping.
1909 mtx_lock(&moea_table_mutex);
1910 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1911 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1912 if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa &&
1913 (pvo->pvo_pte.pte_lo & PTE_PP) ==
1914 (pte_lo & PTE_PP)) {
1915 mtx_unlock(&moea_table_mutex);
1918 moea_pvo_remove(pvo, -1);
1924 * If we aren't overwriting a mapping, try to allocate.
1926 if (moea_initialized) {
1927 pvo = uma_zalloc(zone, M_NOWAIT);
1929 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1930 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1931 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1932 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1934 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1935 moea_bpvo_pool_index++;
1940 mtx_unlock(&moea_table_mutex);
1945 pvo->pvo_vaddr = va;
1947 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1948 pvo->pvo_vaddr &= ~ADDR_POFF;
1949 if (flags & VM_PROT_EXECUTE)
1950 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1951 if (flags & PVO_WIRED)
1952 pvo->pvo_vaddr |= PVO_WIRED;
1953 if (pvo_head != &moea_pvo_kunmanaged)
1954 pvo->pvo_vaddr |= PVO_MANAGED;
1956 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1957 if (flags & PVO_FAKE)
1958 pvo->pvo_vaddr |= PVO_FAKE;
1960 moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo);
1963 * Remember if the list was empty and therefore will be the first
1966 if (LIST_FIRST(pvo_head) == NULL)
1968 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1970 if (pvo->pvo_pte.pte_lo & PVO_WIRED)
1971 pm->pm_stats.wired_count++;
1972 pm->pm_stats.resident_count++;
1975 * We hope this succeeds but it isn't required.
1977 i = moea_pte_insert(ptegidx, &pvo->pvo_pte);
1979 PVO_PTEGIDX_SET(pvo, i);
1981 panic("moea_pvo_enter: overflow");
1982 moea_pte_overflow++;
1984 mtx_unlock(&moea_table_mutex);
1986 return (first ? ENOENT : 0);
1990 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
1995 * If there is an active pte entry, we need to deactivate it (and
1996 * save the ref & cfg bits).
1998 pt = moea_pvo_to_pte(pvo, pteidx);
2000 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
2001 mtx_unlock(&moea_table_mutex);
2002 PVO_PTEGIDX_CLR(pvo);
2004 moea_pte_overflow--;
2008 * Update our statistics.
2010 pvo->pvo_pmap->pm_stats.resident_count--;
2011 if (pvo->pvo_pte.pte_lo & PVO_WIRED)
2012 pvo->pvo_pmap->pm_stats.wired_count--;
2015 * Save the REF/CHG bits into their cache if the page is managed.
2017 if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) {
2020 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
2022 moea_attr_save(pg, pvo->pvo_pte.pte_lo &
2023 (PTE_REF | PTE_CHG));
2028 * Remove this PVO from the PV list.
2030 LIST_REMOVE(pvo, pvo_vlink);
2033 * Remove this from the overflow list and return it to the pool
2034 * if we aren't going to reuse it.
2036 LIST_REMOVE(pvo, pvo_olink);
2037 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2038 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2039 moea_upvo_zone, pvo);
2041 moea_pvo_remove_calls++;
2045 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2050 * We can find the actual pte entry without searching by grabbing
2051 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2052 * noticing the HID bit.
2054 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2055 if (pvo->pvo_pte.pte_hi & PTE_HID)
2056 pteidx ^= moea_pteg_mask * 8;
2061 static struct pvo_entry *
2062 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2064 struct pvo_entry *pvo;
2069 sr = va_to_sr(pm->pm_sr, va);
2070 ptegidx = va_to_pteg(sr, va);
2072 mtx_lock(&moea_table_mutex);
2073 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2074 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2076 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2080 mtx_unlock(&moea_table_mutex);
2086 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2091 * If we haven't been supplied the ptegidx, calculate it.
2097 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2098 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2099 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2102 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2103 mtx_lock(&moea_table_mutex);
2105 if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2106 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2107 "valid pte index", pvo);
2110 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2111 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2112 "pvo but no valid pte", pvo);
2115 if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2116 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) {
2117 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2118 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2121 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2123 panic("moea_pvo_to_pte: pvo %p pte does not match "
2124 "pte %p in moea_pteg_table", pvo, pt);
2127 mtx_assert(&moea_table_mutex, MA_OWNED);
2131 if (pvo->pvo_pte.pte_hi & PTE_VALID) {
2132 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2133 "moea_pteg_table but valid in pvo", pvo, pt);
2136 mtx_unlock(&moea_table_mutex);
2141 * XXX: THIS STUFF SHOULD BE IN pte.c?
2144 moea_pte_spill(vm_offset_t addr)
2146 struct pvo_entry *source_pvo, *victim_pvo;
2147 struct pvo_entry *pvo;
2156 ptegidx = va_to_pteg(sr, addr);
2159 * Have to substitute some entry. Use the primary hash for this.
2160 * Use low bits of timebase as random generator.
2162 pteg = &moea_pteg_table[ptegidx];
2163 mtx_lock(&moea_table_mutex);
2164 __asm __volatile("mftb %0" : "=r"(i));
2170 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2172 * We need to find a pvo entry for this address.
2174 MOEA_PVO_CHECK(pvo);
2175 if (source_pvo == NULL &&
2176 moea_pte_match(&pvo->pvo_pte, sr, addr,
2177 pvo->pvo_pte.pte_hi & PTE_HID)) {
2179 * Now found an entry to be spilled into the pteg.
2180 * The PTE is now valid, so we know it's active.
2182 j = moea_pte_insert(ptegidx, &pvo->pvo_pte);
2185 PVO_PTEGIDX_SET(pvo, j);
2186 moea_pte_overflow--;
2187 MOEA_PVO_CHECK(pvo);
2188 mtx_unlock(&moea_table_mutex);
2194 if (victim_pvo != NULL)
2199 * We also need the pvo entry of the victim we are replacing
2200 * so save the R & C bits of the PTE.
2202 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2203 moea_pte_compare(pt, &pvo->pvo_pte)) {
2205 if (source_pvo != NULL)
2210 if (source_pvo == NULL) {
2211 mtx_unlock(&moea_table_mutex);
2215 if (victim_pvo == NULL) {
2216 if ((pt->pte_hi & PTE_HID) == 0)
2217 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2221 * If this is a secondary PTE, we need to search it's primary
2222 * pvo bucket for the matching PVO.
2224 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2226 MOEA_PVO_CHECK(pvo);
2228 * We also need the pvo entry of the victim we are
2229 * replacing so save the R & C bits of the PTE.
2231 if (moea_pte_compare(pt, &pvo->pvo_pte)) {
2237 if (victim_pvo == NULL)
2238 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2243 * We are invalidating the TLB entry for the EA we are replacing even
2244 * though it's valid. If we don't, we lose any ref/chg bit changes
2245 * contained in the TLB entry.
2247 source_pvo->pvo_pte.pte_hi &= ~PTE_HID;
2249 moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr);
2250 moea_pte_set(pt, &source_pvo->pvo_pte);
2252 PVO_PTEGIDX_CLR(victim_pvo);
2253 PVO_PTEGIDX_SET(source_pvo, i);
2254 moea_pte_replacements++;
2256 MOEA_PVO_CHECK(victim_pvo);
2257 MOEA_PVO_CHECK(source_pvo);
2259 mtx_unlock(&moea_table_mutex);
2264 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2269 mtx_assert(&moea_table_mutex, MA_OWNED);
2272 * First try primary hash.
2274 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2275 if ((pt->pte_hi & PTE_VALID) == 0) {
2276 pvo_pt->pte_hi &= ~PTE_HID;
2277 moea_pte_set(pt, pvo_pt);
2283 * Now try secondary hash.
2285 ptegidx ^= moea_pteg_mask;
2287 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2288 if ((pt->pte_hi & PTE_VALID) == 0) {
2289 pvo_pt->pte_hi |= PTE_HID;
2290 moea_pte_set(pt, pvo_pt);
2295 panic("moea_pte_insert: overflow");
2300 moea_query_bit(vm_page_t m, int ptebit)
2302 struct pvo_entry *pvo;
2306 if (moea_attr_fetch(m) & ptebit)
2310 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2311 MOEA_PVO_CHECK(pvo); /* sanity check */
2314 * See if we saved the bit off. If so, cache it and return
2317 if (pvo->pvo_pte.pte_lo & ptebit) {
2318 moea_attr_save(m, ptebit);
2319 MOEA_PVO_CHECK(pvo); /* sanity check */
2325 * No luck, now go through the hard part of looking at the PTEs
2326 * themselves. Sync so that any pending REF/CHG bits are flushed to
2330 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2331 MOEA_PVO_CHECK(pvo); /* sanity check */
2334 * See if this pvo has a valid PTE. if so, fetch the
2335 * REF/CHG bits from the valid PTE. If the appropriate
2336 * ptebit is set, cache it and return success.
2338 pt = moea_pvo_to_pte(pvo, -1);
2340 moea_pte_synch(pt, &pvo->pvo_pte);
2341 mtx_unlock(&moea_table_mutex);
2342 if (pvo->pvo_pte.pte_lo & ptebit) {
2343 moea_attr_save(m, ptebit);
2344 MOEA_PVO_CHECK(pvo); /* sanity check */
2354 moea_clear_bit(vm_page_t m, int ptebit, int *origbit)
2357 struct pvo_entry *pvo;
2362 * Clear the cached value.
2364 rv = moea_attr_fetch(m);
2365 moea_attr_clear(m, ptebit);
2368 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2369 * we can reset the right ones). note that since the pvo entries and
2370 * list heads are accessed via BAT0 and are never placed in the page
2371 * table, we don't have to worry about further accesses setting the
2377 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2378 * valid pte clear the ptebit from the valid pte.
2381 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2382 MOEA_PVO_CHECK(pvo); /* sanity check */
2383 pt = moea_pvo_to_pte(pvo, -1);
2385 moea_pte_synch(pt, &pvo->pvo_pte);
2386 if (pvo->pvo_pte.pte_lo & ptebit) {
2388 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2390 mtx_unlock(&moea_table_mutex);
2392 rv |= pvo->pvo_pte.pte_lo;
2393 pvo->pvo_pte.pte_lo &= ~ptebit;
2394 MOEA_PVO_CHECK(pvo); /* sanity check */
2397 if (origbit != NULL) {
2405 * Return true if the physical range is encompassed by the battable[idx]
2408 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2416 * Return immediately if not a valid mapping
2418 if (!battable[idx].batu & BAT_Vs)
2422 * The BAT entry must be cache-inhibited, guarded, and r/w
2423 * so it can function as an i/o page
2425 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2426 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2430 * The address should be within the BAT range. Assume that the
2431 * start address in the BAT has the correct alignment (thus
2432 * not requiring masking)
2434 start = battable[idx].batl & BAT_PBS;
2435 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2436 end = start | (bat_ble << 15) | 0x7fff;
2438 if ((pa < start) || ((pa + size) > end))
2445 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2450 * This currently does not work for entries that
2451 * overlap 256M BAT segments.
2454 for(i = 0; i < 16; i++)
2455 if (moea_bat_mapped(i, pa, size) == 0)
2462 moea_page_executable(mmu_t mmu, vm_page_t pg)
2464 return ((moea_attr_fetch(pg) & PTE_EXEC) == PTE_EXEC);
2468 * Map a set of physical memory pages into the kernel virtual
2469 * address space. Return a pointer to where it is mapped. This
2470 * routine is intended to be used for mapping device memory,
2474 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
2476 vm_offset_t va, tmpva, ppa, offset;
2479 ppa = trunc_page(pa);
2480 offset = pa & PAGE_MASK;
2481 size = roundup(offset + size, PAGE_SIZE);
2486 * If the physical address lies within a valid BAT table entry,
2487 * return the 1:1 mapping. This currently doesn't work
2488 * for regions that overlap 256M BAT segments.
2490 for (i = 0; i < 16; i++) {
2491 if (moea_bat_mapped(i, pa, size) == 0)
2492 return ((void *) pa);
2495 va = kmem_alloc_nofault(kernel_map, size);
2497 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2499 for (tmpva = va; size > 0;) {
2500 moea_kenter(mmu, tmpva, ppa);
2501 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */
2507 return ((void *)(va + offset));
2511 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2513 vm_offset_t base, offset;
2516 * If this is outside kernel virtual space, then it's a
2517 * battable entry and doesn't require unmapping
2519 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2520 base = trunc_page(va);
2521 offset = va & PAGE_MASK;
2522 size = roundup(offset + size, PAGE_SIZE);
2523 kmem_free(kernel_map, base, size);