2 * Copyright (c) 2008 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
35 #include <sys/cpuset.h>
37 #include <sys/malloc.h>
38 #include <sys/mutex.h>
41 #include <sys/sched.h>
45 #include <vm/vm_param.h>
47 #include <vm/vm_map.h>
48 #include <vm/vm_extern.h>
49 #include <vm/vm_kern.h>
51 #include <machine/bus.h>
52 #include <machine/cpu.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/pcb.h>
55 #include <machine/platform.h>
56 #include <machine/md_var.h>
57 #include <machine/setjmp.h>
58 #include <machine/smp.h>
62 extern struct pcpu __pcpu[MAXCPU];
64 volatile static int ap_awake;
65 volatile static u_int ap_letgo;
66 volatile static u_quad_t ap_timebase;
67 static u_int ipi_msg_cnt[32];
68 static struct mtx ap_boot_mtx;
69 struct pcb stoppcbs[MAXCPU];
72 machdep_ap_bootstrap(void)
76 PCPU_SET(pir, mfspr(SPR_PIR));
78 __asm __volatile("msync; isync");
83 /* Initialize DEC and TB, sync with the BSP values */
85 /* Writing to the time base register is hypervisor-privileged */
93 /* Give platform code a chance to do anything necessary */
94 platform_smp_ap_init();
96 /* Serialize console output and AP count increment */
97 mtx_lock_spin(&ap_boot_mtx);
99 printf("SMP: AP CPU #%d launched\n", PCPU_GET(cpuid));
100 mtx_unlock_spin(&ap_boot_mtx);
102 /* Start per-CPU event timers. */
105 /* Announce ourselves awake, and enter the scheduler */
110 cpu_mp_setmaxid(void)
112 struct cpuref cpuref;
116 error = platform_smp_first_cpu(&cpuref);
119 error = platform_smp_next_cpu(&cpuref);
126 * Set the largest cpuid we're going to use. This is necessary
127 * for VM initialization.
129 mp_maxid = min(mp_ncpus, MAXCPU) - 1;
137 * We're not going to enable SMP if there's only 1 processor.
139 return (mp_ncpus > 1);
145 struct cpuref bsp, cpu;
149 error = platform_smp_get_bsp(&bsp);
150 KASSERT(error == 0, ("Don't know BSP"));
151 KASSERT(bsp.cr_cpuid == 0, ("%s: cpuid != 0", __func__));
153 error = platform_smp_first_cpu(&cpu);
155 if (cpu.cr_cpuid >= MAXCPU) {
156 printf("SMP: cpu%d: skipped -- ID out of range\n",
160 if (CPU_ISSET(cpu.cr_cpuid, &all_cpus)) {
161 printf("SMP: cpu%d: skipped - duplicate ID\n",
165 if (cpu.cr_cpuid != bsp.cr_cpuid) {
168 pc = &__pcpu[cpu.cr_cpuid];
169 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
171 pcpu_init(pc, cpu.cr_cpuid, sizeof(*pc));
172 dpcpu_init(dpcpu, cpu.cr_cpuid);
175 pc->pc_cpuid = bsp.cr_cpuid;
178 pc->pc_hwref = cpu.cr_hwref;
179 CPU_SET(pc->pc_cpuid, &all_cpus);
181 error = platform_smp_next_cpu(&cpu);
186 cpu_mp_announce(void)
191 for (i = 0; i <= mp_maxid; i++) {
195 printf("cpu%d: dev=%x", i, (int)pc->pc_hwref);
203 cpu_mp_unleash(void *dummy)
211 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
215 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
219 printf("Waking up CPU %d (dev=%x)\n",
220 pc->pc_cpuid, (int)pc->pc_hwref);
222 platform_smp_start_cpu(pc);
224 timeout = 2000; /* wait 2sec for the AP */
225 while (!pc->pc_awake && --timeout > 0)
229 PCPU_SET(pir, mfspr(SPR_PIR));
234 printf("Adding CPU %d, pir=%x, awake=%x\n",
235 pc->pc_cpuid, pc->pc_pir, pc->pc_awake);
238 CPU_SET(pc->pc_cpuid, &stopped_cpus);
243 /* Provide our current DEC and TB values for APs */
244 ap_timebase = mftb() + 10;
245 __asm __volatile("msync; isync");
247 /* Let APs continue */
248 atomic_store_rel_int(&ap_letgo, 1);
251 /* Writing to the time base register is hypervisor-privileged */
252 if (mfmsr() & PSL_HV)
258 while (ap_awake < smp_cpus)
261 if (smp_cpus != cpus || cpus != mp_ncpus) {
262 printf("SMP: %d CPUs found; %d CPUs usable; %d CPUs woken\n",
263 mp_ncpus, cpus, smp_cpus);
266 /* Let the APs get into the scheduler */
269 /* XXX Atomic set operation? */
273 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL);
276 powerpc_ipi_handler(void *arg)
282 CTR2(KTR_SMP, "%s: MSR 0x%08x", __func__, mfmsr());
284 ipimask = atomic_readandclear_32(&(pcpup->pc_ipimask));
286 return (FILTER_STRAY);
287 while ((msg = ffs(ipimask) - 1) != -1) {
288 ipimask &= ~(1u << msg);
292 CTR1(KTR_SMP, "%s: IPI_AST", __func__);
295 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
296 sched_preempt(curthread);
299 CTR1(KTR_SMP, "%s: IPI_RENDEZVOUS", __func__);
300 smp_rendezvous_action();
305 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
306 * necessary to add such case in the switch.
308 CTR1(KTR_SMP, "%s: IPI_STOP or IPI_STOP_HARD (stop)",
310 cpuid = PCPU_GET(cpuid);
311 savectx(&stoppcbs[cpuid]);
312 savectx(PCPU_GET(curpcb));
313 CPU_SET_ATOMIC(cpuid, &stopped_cpus);
314 while (!CPU_ISSET(cpuid, &started_cpus))
316 CPU_CLR_ATOMIC(cpuid, &stopped_cpus);
317 CPU_CLR_ATOMIC(cpuid, &started_cpus);
318 CTR1(KTR_SMP, "%s: IPI_STOP (restart)", __func__);
321 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
327 return (FILTER_HANDLED);
331 ipi_send(struct pcpu *pc, int ipi)
334 CTR4(KTR_SMP, "%s: pc=%p, targetcpu=%d, IPI=%d", __func__,
335 pc, pc->pc_cpuid, ipi);
337 atomic_set_32(&pc->pc_ipimask, (1 << ipi));
339 PIC_IPI(root_pic, pc->pc_cpuid);
341 CTR1(KTR_SMP, "%s: sent", __func__);
344 /* Send an IPI to a set of cpus. */
346 ipi_selected(cpuset_t cpus, int ipi)
350 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
351 if (CPU_ISSET(pc->pc_cpuid, &cpus))
356 /* Send an IPI to a specific CPU. */
358 ipi_cpu(int cpu, u_int ipi)
361 ipi_send(cpuid_to_pcpu[cpu], ipi);
364 /* Send an IPI to all CPUs EXCEPT myself. */
366 ipi_all_but_self(int ipi)
370 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {