sys/powerpc/powerpc/openpic.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2002 Benno Rice.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  21  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  22  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  23  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  24  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  25  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/conf.h>
  34 #include <sys/kernel.h>
  35 #include <sys/proc.h>
  36 #include <sys/rman.h>
  37 #include <sys/sched.h>
  38
  39 #include <machine/bus.h>
  40 #include <machine/intr_machdep.h>
  41 #include <machine/md_var.h>
  42 #include <machine/pio.h>
  43 #include <machine/resource.h>
  44
  45 #include <vm/vm.h>
  46 #include <vm/pmap.h>
  47
  48 #include <machine/openpicreg.h>
  49 #include <machine/openpicvar.h>
  50
  51 #include "pic_if.h"
  52
  53 devclass_t openpic_devclass;
  54
  55 /*
  56  * Local routines
  57  */
  58 static int openpic_intr(void *arg);
  59
  60 static __inline uint32_t
  61 openpic_read(struct openpic_softc *sc, u_int reg)
  62 {
  63         return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
  64 }
  65
  66 static __inline void
  67 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
  68 {
  69         bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
  70 }
  71
  72 static __inline void
  73 openpic_set_priority(struct openpic_softc *sc, int pri)
  74 {
  75         u_int tpr;
  76         uint32_t x;
  77
  78         sched_pin();
  79         tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
  80         x = openpic_read(sc, tpr);
  81         x &= ~OPENPIC_TPR_MASK;
  82         x |= pri;
  83         openpic_write(sc, tpr, x);
  84         sched_unpin();
  85 }
  86
  87 int
  88 openpic_common_attach(device_t dev, uint32_t node)
  89 {
  90         struct openpic_softc *sc;
  91         u_int     cpu, ipi, irq;
  92         u_int32_t x;
  93
  94         sc = device_get_softc(dev);
  95         sc->sc_dev = dev;
  96
  97         sc->sc_rid = 0;
  98         sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
  99             RF_ACTIVE);
 100
 101         if (sc->sc_memr == NULL) {
 102                 device_printf(dev, "Could not alloc mem resource!\n");
 103                 return (ENXIO);
 104         }
 105
 106         sc->sc_bt = rman_get_bustag(sc->sc_memr);
 107         sc->sc_bh = rman_get_bushandle(sc->sc_memr);
 108
 109         /* Reset the PIC */
 110         x = openpic_read(sc, OPENPIC_CONFIG);
 111         x |= OPENPIC_CONFIG_RESET;
 112         openpic_write(sc, OPENPIC_CONFIG, x);
 113
 114         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 115                 powerpc_sync();
 116                 DELAY(100);
 117         }
 118
 119         /* Check if this is a cascaded PIC */
 120         sc->sc_irq = 0;
 121         sc->sc_intr = NULL;
 122         do {
 123                 struct resource_list *rl;
 124
 125                 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
 126                 if (rl == NULL)
 127                         break;
 128                 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
 129                         break;
 130
 131                 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 132                     &sc->sc_irq, RF_ACTIVE);
 133
 134                 /* XXX Cascaded PICs pass NULL trapframes! */
 135                 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
 136                     openpic_intr, NULL, dev, &sc->sc_icookie);
 137         } while (0);
 138
 139         /* Reset the PIC */
 140         x = openpic_read(sc, OPENPIC_CONFIG);
 141         x |= OPENPIC_CONFIG_RESET;
 142         openpic_write(sc, OPENPIC_CONFIG, x);
 143
 144         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 145                 powerpc_sync();
 146                 DELAY(100);
 147         }
 148
 149         x = openpic_read(sc, OPENPIC_FEATURE);
 150         switch (x & OPENPIC_FEATURE_VERSION_MASK) {
 151         case 1:
 152                 sc->sc_version = "1.0";
 153                 break;
 154         case 2:
 155                 sc->sc_version = "1.2";
 156                 break;
 157         case 3:
 158                 sc->sc_version = "1.3";
 159                 break;
 160         default:
 161                 sc->sc_version = "unknown";
 162                 break;
 163         }
 164
 165         sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
 166             OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
 167         sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
 168             OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
 169
 170         /*
 171          * PSIM seems to report 1 too many IRQs and CPUs
 172          */
 173         if (sc->sc_psim) {
 174                 sc->sc_nirq--;
 175                 sc->sc_ncpu--;
 176         }
 177
 178         if (bootverbose)
 179                 device_printf(dev,
 180                     "Version %s, supports %d CPUs and %d irqs\n",
 181                     sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
 182
 183         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 184                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
 185
 186         /* Reset and disable all interrupts. */
 187         for (irq = 0; irq < sc->sc_nirq; irq++) {
 188                 x = irq;                /* irq == vector. */
 189                 x |= OPENPIC_IMASK;
 190                 x |= OPENPIC_POLARITY_NEGATIVE;
 191                 x |= OPENPIC_SENSE_LEVEL;
 192                 x |= 8 << OPENPIC_PRIORITY_SHIFT;
 193                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 194         }
 195
 196         /* Reset and disable all IPIs. */
 197         for (ipi = 0; ipi < 4; ipi++) {
 198                 x = sc->sc_nirq + ipi;
 199                 x |= OPENPIC_IMASK;
 200                 x |= 15 << OPENPIC_PRIORITY_SHIFT;
 201                 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
 202         }
 203
 204         /* we don't need 8259 passthrough mode */
 205         x = openpic_read(sc, OPENPIC_CONFIG);
 206         x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
 207         openpic_write(sc, OPENPIC_CONFIG, x);
 208
 209         /* send all interrupts to cpu 0 */
 210         for (irq = 0; irq < sc->sc_nirq; irq++)
 211                 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
 212
 213         /* clear all pending interrupts from cpu 0 */
 214         for (irq = 0; irq < sc->sc_nirq; irq++) {
 215                 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
 216                 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
 217         }
 218
 219         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 220                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
 221
 222         powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
 223
 224         /* If this is not a cascaded PIC, it must be the root PIC */
 225         if (sc->sc_intr == NULL)
 226                 root_pic = dev;
 227
 228         return (0);
 229 }
 230
 231 /*
 232  * PIC I/F methods
 233  */
 234
 235 void
 236 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask)
 237 {
 238         struct openpic_softc *sc;
 239
 240         /* If we aren't directly connected to the CPU, this won't work */
 241         if (dev != root_pic)
 242                 return;
 243
 244         sc = device_get_softc(dev);
 245
 246         /*
 247          * XXX: openpic_write() is very special and just needs a 32 bits mask.
 248          * For the moment, just play dirty and get the first half word.
 249          */
 250         openpic_write(sc, OPENPIC_IDEST(irq), cpumask.__bits[0] & 0xffffffff);
 251 }
 252
 253 void
 254 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
 255     enum intr_polarity pol)
 256 {
 257         struct openpic_softc *sc;
 258         uint32_t x;
 259
 260         sc = device_get_softc(dev);
 261         x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 262         if (pol == INTR_POLARITY_LOW)
 263                 x &= ~OPENPIC_POLARITY_POSITIVE;
 264         else
 265                 x |= OPENPIC_POLARITY_POSITIVE;
 266         if (trig == INTR_TRIGGER_EDGE)
 267                 x &= ~OPENPIC_SENSE_LEVEL;
 268         else
 269                 x |= OPENPIC_SENSE_LEVEL;
 270         openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 271 }
 272
 273 static int
 274 openpic_intr(void *arg)
 275 {
 276         device_t dev = (device_t)(arg);
 277
 278         /* XXX Cascaded PICs do not pass non-NULL trapframes! */
 279         openpic_dispatch(dev, NULL);
 280
 281         return (FILTER_HANDLED);
 282 }
 283
 284 void
 285 openpic_dispatch(device_t dev, struct trapframe *tf)
 286 {
 287         struct openpic_softc *sc;
 288         u_int cpuid, vector;
 289
 290         CTR1(KTR_INTR, "%s: got interrupt", __func__);
 291
 292         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 293
 294         sc = device_get_softc(dev);
 295         while (1) {
 296                 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
 297                 vector &= OPENPIC_VECTOR_MASK;
 298                 if (vector == 255)
 299                         break;
 300                 powerpc_dispatch_intr(vector, tf);
 301         }
 302 }
 303
 304 void
 305 openpic_enable(device_t dev, u_int irq, u_int vector)
 306 {
 307         struct openpic_softc *sc;
 308         uint32_t x;
 309
 310         sc = device_get_softc(dev);
 311         if (irq < sc->sc_nirq) {
 312                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 313                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 314                 x |= vector;
 315                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 316         } else {
 317                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 318                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 319                 x |= vector;
 320                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 321         }
 322 }
 323
 324 void
 325 openpic_eoi(device_t dev, u_int irq __unused)
 326 {
 327         struct openpic_softc *sc;
 328         u_int cpuid;
 329
 330         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 331
 332         sc = device_get_softc(dev);
 333         openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
 334 }
 335
 336 void
 337 openpic_ipi(device_t dev, u_int cpu)
 338 {
 339         struct openpic_softc *sc;
 340
 341         KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
 342
 343         sc = device_get_softc(dev);
 344         sched_pin();
 345         openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
 346             1u << cpu);
 347         sched_unpin();
 348 }
 349
 350 void
 351 openpic_mask(device_t dev, u_int irq)
 352 {
 353         struct openpic_softc *sc;
 354         uint32_t x;
 355
 356         sc = device_get_softc(dev);
 357         if (irq < sc->sc_nirq) {
 358                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 359                 x |= OPENPIC_IMASK;
 360                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 361         } else {
 362                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 363                 x |= OPENPIC_IMASK;
 364                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 365         }
 366 }
 367
 368 void
 369 openpic_unmask(device_t dev, u_int irq)
 370 {
 371         struct openpic_softc *sc;
 372         uint32_t x;
 373
 374         sc = device_get_softc(dev);
 375         if (irq < sc->sc_nirq) {
 376                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 377                 x &= ~OPENPIC_IMASK;
 378                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 379         } else {
 380                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 381                 x &= ~OPENPIC_IMASK;
 382                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 383         }
 384 }
 385
 386 int
 387 openpic_suspend(device_t dev)
 388 {
 389         struct openpic_softc *sc;
 390         int i;
 391
 392         sc = device_get_softc(dev);
 393
 394         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 395         for (i = 0; i < 4; i++) {
 396                 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
 397         }
 398
 399         for (i = 0; i < 4; i++) {
 400                 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
 401         }
 402
 403         for (i = 0; i < OPENPIC_TIMERS; i++) {
 404                 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
 405                 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
 406                 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
 407                 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
 408         }
 409
 410         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 411                 sc->sc_saved_vectors[i] =
 412                     bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
 413
 414         return (0);
 415 }
 416
 417 int
 418 openpic_resume(device_t dev)
 419 {
 420         struct openpic_softc *sc;
 421         int i;
 422
 423         sc = device_get_softc(dev);
 424
 425         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 426         for (i = 0; i < 4; i++) {
 427                 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
 428         }
 429
 430         for (i = 0; i < 4; i++) {
 431                 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
 432         }
 433
 434         for (i = 0; i < OPENPIC_TIMERS; i++) {
 435                 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
 436                 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
 437                 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
 438                 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
 439         }
 440
 441         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 442                 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);
 443
 444         return (0);
 445 }