2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2002 Benno Rice.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/sched.h>
39 #include <machine/bus.h>
40 #include <machine/intr_machdep.h>
41 #include <machine/md_var.h>
42 #include <machine/pio.h>
43 #include <machine/resource.h>
48 #include <machine/openpicreg.h>
49 #include <machine/openpicvar.h>
53 devclass_t openpic_devclass;
58 static int openpic_intr(void *arg);
60 static __inline uint32_t
61 openpic_read(struct openpic_softc *sc, u_int reg)
63 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
67 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
69 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
73 openpic_set_priority(struct openpic_softc *sc, int pri)
79 tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
80 x = openpic_read(sc, tpr);
81 x &= ~OPENPIC_TPR_MASK;
83 openpic_write(sc, tpr, x);
88 openpic_common_attach(device_t dev, uint32_t node)
90 struct openpic_softc *sc;
94 sc = device_get_softc(dev);
98 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
101 if (sc->sc_memr == NULL) {
102 device_printf(dev, "Could not alloc mem resource!\n");
106 sc->sc_bt = rman_get_bustag(sc->sc_memr);
107 sc->sc_bh = rman_get_bushandle(sc->sc_memr);
110 x = openpic_read(sc, OPENPIC_CONFIG);
111 x |= OPENPIC_CONFIG_RESET;
112 openpic_write(sc, OPENPIC_CONFIG, x);
114 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
119 /* Check if this is a cascaded PIC */
123 struct resource_list *rl;
125 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
128 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
131 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
132 &sc->sc_irq, RF_ACTIVE);
134 /* XXX Cascaded PICs pass NULL trapframes! */
135 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
136 openpic_intr, NULL, dev, &sc->sc_icookie);
140 x = openpic_read(sc, OPENPIC_CONFIG);
141 x |= OPENPIC_CONFIG_RESET;
142 openpic_write(sc, OPENPIC_CONFIG, x);
144 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
149 x = openpic_read(sc, OPENPIC_FEATURE);
150 switch (x & OPENPIC_FEATURE_VERSION_MASK) {
152 sc->sc_version = "1.0";
155 sc->sc_version = "1.2";
158 sc->sc_version = "1.3";
161 sc->sc_version = "unknown";
165 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
166 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
167 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
168 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
171 * PSIM seems to report 1 too many IRQs and CPUs
180 "Version %s, supports %d CPUs and %d irqs\n",
181 sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
183 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
184 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
186 /* Reset and disable all interrupts. */
187 for (irq = 0; irq < sc->sc_nirq; irq++) {
188 x = irq; /* irq == vector. */
190 x |= OPENPIC_POLARITY_NEGATIVE;
191 x |= OPENPIC_SENSE_LEVEL;
192 x |= 8 << OPENPIC_PRIORITY_SHIFT;
193 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
196 /* Reset and disable all IPIs. */
197 for (ipi = 0; ipi < 4; ipi++) {
198 x = sc->sc_nirq + ipi;
200 x |= 15 << OPENPIC_PRIORITY_SHIFT;
201 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
204 /* we don't need 8259 passthrough mode */
205 x = openpic_read(sc, OPENPIC_CONFIG);
206 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
207 openpic_write(sc, OPENPIC_CONFIG, x);
209 /* send all interrupts to cpu 0 */
210 for (irq = 0; irq < sc->sc_nirq; irq++)
211 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
213 /* clear all pending interrupts from cpu 0 */
214 for (irq = 0; irq < sc->sc_nirq; irq++) {
215 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
216 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
219 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
220 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
222 powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
224 /* If this is not a cascaded PIC, it must be the root PIC */
225 if (sc->sc_intr == NULL)
236 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask)
238 struct openpic_softc *sc;
240 /* If we aren't directly connected to the CPU, this won't work */
244 sc = device_get_softc(dev);
247 * XXX: openpic_write() is very special and just needs a 32 bits mask.
248 * For the moment, just play dirty and get the first half word.
250 openpic_write(sc, OPENPIC_IDEST(irq), cpumask.__bits[0] & 0xffffffff);
254 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
255 enum intr_polarity pol)
257 struct openpic_softc *sc;
260 sc = device_get_softc(dev);
261 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
262 if (pol == INTR_POLARITY_LOW)
263 x &= ~OPENPIC_POLARITY_POSITIVE;
265 x |= OPENPIC_POLARITY_POSITIVE;
266 if (trig == INTR_TRIGGER_EDGE)
267 x &= ~OPENPIC_SENSE_LEVEL;
269 x |= OPENPIC_SENSE_LEVEL;
270 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
274 openpic_intr(void *arg)
276 device_t dev = (device_t)(arg);
278 /* XXX Cascaded PICs do not pass non-NULL trapframes! */
279 openpic_dispatch(dev, NULL);
281 return (FILTER_HANDLED);
285 openpic_dispatch(device_t dev, struct trapframe *tf)
287 struct openpic_softc *sc;
290 CTR1(KTR_INTR, "%s: got interrupt", __func__);
292 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
294 sc = device_get_softc(dev);
296 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
297 vector &= OPENPIC_VECTOR_MASK;
300 powerpc_dispatch_intr(vector, tf);
305 openpic_enable(device_t dev, u_int irq, u_int vector)
307 struct openpic_softc *sc;
310 sc = device_get_softc(dev);
311 if (irq < sc->sc_nirq) {
312 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
313 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
315 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
317 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
318 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
320 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
325 openpic_eoi(device_t dev, u_int irq __unused)
327 struct openpic_softc *sc;
330 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
332 sc = device_get_softc(dev);
333 openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
337 openpic_ipi(device_t dev, u_int cpu)
339 struct openpic_softc *sc;
341 KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
343 sc = device_get_softc(dev);
345 openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
351 openpic_mask(device_t dev, u_int irq)
353 struct openpic_softc *sc;
356 sc = device_get_softc(dev);
357 if (irq < sc->sc_nirq) {
358 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
360 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
362 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
364 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
369 openpic_unmask(device_t dev, u_int irq)
371 struct openpic_softc *sc;
374 sc = device_get_softc(dev);
375 if (irq < sc->sc_nirq) {
376 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
378 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
380 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
382 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
387 openpic_suspend(device_t dev)
389 struct openpic_softc *sc;
392 sc = device_get_softc(dev);
394 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
395 for (i = 0; i < 4; i++) {
396 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
399 for (i = 0; i < 4; i++) {
400 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
403 for (i = 0; i < OPENPIC_TIMERS; i++) {
404 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
405 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
406 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
407 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
410 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
411 sc->sc_saved_vectors[i] =
412 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
418 openpic_resume(device_t dev)
420 struct openpic_softc *sc;
423 sc = device_get_softc(dev);
425 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
426 for (i = 0; i < 4; i++) {
427 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
430 for (i = 0; i < 4; i++) {
431 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
434 for (i = 0; i < OPENPIC_TIMERS; i++) {
435 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
436 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
437 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
438 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
441 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
442 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);