sys/powerpc/powerpc/openpic.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2002 Benno Rice.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  21  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  22  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  23  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  24  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  25  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/conf.h>
  34 #include <sys/kernel.h>
  35 #include <sys/ktr.h>
  36 #include <sys/proc.h>
  37 #include <sys/rman.h>
  38 #include <sys/sched.h>
  39 #include <sys/smp.h>
  40
  41 #include <machine/bus.h>
  42 #include <machine/intr_machdep.h>
  43 #include <machine/md_var.h>
  44 #include <machine/pio.h>
  45 #include <machine/resource.h>
  46
  47 #include <vm/vm.h>
  48 #include <vm/pmap.h>
  49
  50 #include <machine/openpicreg.h>
  51 #include <machine/openpicvar.h>
  52
  53 #include "pic_if.h"
  54
  55 devclass_t openpic_devclass;
  56
  57 /*
  58  * Local routines
  59  */
  60 static int openpic_intr(void *arg);
  61
  62 static __inline uint32_t
  63 openpic_read(struct openpic_softc *sc, u_int reg)
  64 {
  65         return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
  66 }
  67
  68 static __inline void
  69 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
  70 {
  71         bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
  72 }
  73
  74 static __inline void
  75 openpic_set_priority(struct openpic_softc *sc, int pri)
  76 {
  77         u_int tpr;
  78         uint32_t x;
  79
  80         sched_pin();
  81         tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
  82         x = openpic_read(sc, tpr);
  83         x &= ~OPENPIC_TPR_MASK;
  84         x |= pri;
  85         openpic_write(sc, tpr, x);
  86         sched_unpin();
  87 }
  88
  89 int
  90 openpic_common_attach(device_t dev, uint32_t node)
  91 {
  92         struct openpic_softc *sc;
  93         u_int     cpu, ipi, irq;
  94         u_int32_t x;
  95
  96         sc = device_get_softc(dev);
  97         sc->sc_dev = dev;
  98
  99         sc->sc_rid = 0;
 100         sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
 101             RF_ACTIVE);
 102
 103         if (sc->sc_memr == NULL) {
 104                 device_printf(dev, "Could not alloc mem resource!\n");
 105                 return (ENXIO);
 106         }
 107
 108         sc->sc_bt = rman_get_bustag(sc->sc_memr);
 109         sc->sc_bh = rman_get_bushandle(sc->sc_memr);
 110
 111         /* Reset the PIC */
 112         x = openpic_read(sc, OPENPIC_CONFIG);
 113         x |= OPENPIC_CONFIG_RESET;
 114         openpic_write(sc, OPENPIC_CONFIG, x);
 115
 116         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 117                 powerpc_sync();
 118                 DELAY(100);
 119         }
 120
 121         /* Check if this is a cascaded PIC */
 122         sc->sc_irq = 0;
 123         sc->sc_intr = NULL;
 124         do {
 125                 struct resource_list *rl;
 126
 127                 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
 128                 if (rl == NULL)
 129                         break;
 130                 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
 131                         break;
 132
 133                 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 134                     &sc->sc_irq, RF_ACTIVE);
 135
 136                 /* XXX Cascaded PICs pass NULL trapframes! */
 137                 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
 138                     openpic_intr, NULL, dev, &sc->sc_icookie);
 139         } while (0);
 140
 141         /* Reset the PIC */
 142         x = openpic_read(sc, OPENPIC_CONFIG);
 143         x |= OPENPIC_CONFIG_RESET;
 144         openpic_write(sc, OPENPIC_CONFIG, x);
 145
 146         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 147                 powerpc_sync();
 148                 DELAY(100);
 149         }
 150
 151         x = openpic_read(sc, OPENPIC_FEATURE);
 152         switch (x & OPENPIC_FEATURE_VERSION_MASK) {
 153         case 1:
 154                 sc->sc_version = "1.0";
 155                 break;
 156         case 2:
 157                 sc->sc_version = "1.2";
 158                 break;
 159         case 3:
 160                 sc->sc_version = "1.3";
 161                 break;
 162         default:
 163                 sc->sc_version = "unknown";
 164                 break;
 165         }
 166
 167         sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
 168             OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
 169         sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
 170             OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
 171
 172         /*
 173          * PSIM seems to report 1 too many IRQs and CPUs
 174          */
 175         if (sc->sc_psim) {
 176                 sc->sc_nirq--;
 177                 sc->sc_ncpu--;
 178         }
 179
 180         if (bootverbose)
 181                 device_printf(dev,
 182                     "Version %s, supports %d CPUs and %d irqs\n",
 183                     sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
 184
 185         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 186                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
 187
 188         /* Reset and disable all interrupts. */
 189         for (irq = 0; irq < sc->sc_nirq; irq++) {
 190                 x = irq;                /* irq == vector. */
 191                 x |= OPENPIC_IMASK;
 192                 x |= OPENPIC_POLARITY_NEGATIVE;
 193                 x |= OPENPIC_SENSE_LEVEL;
 194                 x |= 8 << OPENPIC_PRIORITY_SHIFT;
 195                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 196         }
 197
 198         /* Reset and disable all IPIs. */
 199         for (ipi = 0; ipi < 4; ipi++) {
 200                 x = sc->sc_nirq + ipi;
 201                 x |= OPENPIC_IMASK;
 202                 x |= 15 << OPENPIC_PRIORITY_SHIFT;
 203                 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
 204         }
 205
 206         /* we don't need 8259 passthrough mode */
 207         x = openpic_read(sc, OPENPIC_CONFIG);
 208         x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
 209         openpic_write(sc, OPENPIC_CONFIG, x);
 210
 211         /* send all interrupts to cpu 0 */
 212         for (irq = 0; irq < sc->sc_nirq; irq++)
 213                 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
 214
 215         /* clear all pending interrupts from cpu 0 */
 216         for (irq = 0; irq < sc->sc_nirq; irq++) {
 217                 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
 218                 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
 219         }
 220
 221         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 222                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
 223
 224         powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
 225
 226         /* If this is not a cascaded PIC, it must be the root PIC */
 227         if (sc->sc_intr == NULL)
 228                 root_pic = dev;
 229
 230         return (0);
 231 }
 232
 233 /*
 234  * PIC I/F methods
 235  */
 236
 237 void
 238 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
 239 {
 240         struct openpic_softc *sc;
 241         uint32_t mask;
 242
 243         /* If we aren't directly connected to the CPU, this won't work */
 244         if (dev != root_pic)
 245                 return;
 246
 247         sc = device_get_softc(dev);
 248
 249         /*
 250          * XXX: openpic_write() is very special and just needs a 32 bits mask.
 251          * For the moment, just play dirty and get the first half word.
 252          */
 253         mask = cpumask.__bits[0] & 0xffffffff;
 254         if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
 255                 int i = mftb() % CPU_COUNT(&cpumask);
 256                 int cpu, ncpu;
 257
 258                 ncpu = 0;
 259                 CPU_FOREACH(cpu) {
 260                         if (!(mask & (1 << cpu)))
 261                                 continue;
 262                         if (ncpu == i)
 263                                 break;
 264                         ncpu++;
 265                 }
 266                 mask &= (1 << cpu);
 267         }
 268
 269         openpic_write(sc, OPENPIC_IDEST(irq), mask);
 270 }
 271
 272 void
 273 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
 274     enum intr_polarity pol)
 275 {
 276         struct openpic_softc *sc;
 277         uint32_t x;
 278
 279         sc = device_get_softc(dev);
 280         x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 281         if (pol == INTR_POLARITY_LOW)
 282                 x &= ~OPENPIC_POLARITY_POSITIVE;
 283         else
 284                 x |= OPENPIC_POLARITY_POSITIVE;
 285         if (trig == INTR_TRIGGER_EDGE)
 286                 x &= ~OPENPIC_SENSE_LEVEL;
 287         else
 288                 x |= OPENPIC_SENSE_LEVEL;
 289         openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 290 }
 291
 292 static int
 293 openpic_intr(void *arg)
 294 {
 295         device_t dev = (device_t)(arg);
 296
 297         /* XXX Cascaded PICs do not pass non-NULL trapframes! */
 298         openpic_dispatch(dev, NULL);
 299
 300         return (FILTER_HANDLED);
 301 }
 302
 303 void
 304 openpic_dispatch(device_t dev, struct trapframe *tf)
 305 {
 306         struct openpic_softc *sc;
 307         u_int cpuid, vector;
 308
 309         CTR1(KTR_INTR, "%s: got interrupt", __func__);
 310
 311         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 312
 313         sc = device_get_softc(dev);
 314         while (1) {
 315                 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
 316                 vector &= OPENPIC_VECTOR_MASK;
 317                 if (vector == 255)
 318                         break;
 319                 powerpc_dispatch_intr(vector, tf);
 320         }
 321 }
 322
 323 void
 324 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
 325 {
 326         struct openpic_softc *sc;
 327         uint32_t x;
 328
 329         sc = device_get_softc(dev);
 330         if (irq < sc->sc_nirq) {
 331                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 332                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 333                 x |= vector;
 334                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 335         } else {
 336                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 337                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 338                 x |= vector;
 339                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 340         }
 341 }
 342
 343 void
 344 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
 345 {
 346         struct openpic_softc *sc;
 347         u_int cpuid;
 348
 349         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 350
 351         sc = device_get_softc(dev);
 352         openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
 353 }
 354
 355 void
 356 openpic_ipi(device_t dev, u_int cpu)
 357 {
 358         struct openpic_softc *sc;
 359
 360         KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
 361
 362         sc = device_get_softc(dev);
 363         sched_pin();
 364         openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
 365             1u << cpu);
 366         sched_unpin();
 367 }
 368
 369 void
 370 openpic_mask(device_t dev, u_int irq, void *priv __unused)
 371 {
 372         struct openpic_softc *sc;
 373         uint32_t x;
 374
 375         sc = device_get_softc(dev);
 376         if (irq < sc->sc_nirq) {
 377                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 378                 x |= OPENPIC_IMASK;
 379                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 380         } else {
 381                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 382                 x |= OPENPIC_IMASK;
 383                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 384         }
 385 }
 386
 387 void
 388 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
 389 {
 390         struct openpic_softc *sc;
 391         uint32_t x;
 392
 393         sc = device_get_softc(dev);
 394         if (irq < sc->sc_nirq) {
 395                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 396                 x &= ~OPENPIC_IMASK;
 397                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 398         } else {
 399                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 400                 x &= ~OPENPIC_IMASK;
 401                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 402         }
 403 }
 404
 405 int
 406 openpic_suspend(device_t dev)
 407 {
 408         struct openpic_softc *sc;
 409         int i;
 410
 411         sc = device_get_softc(dev);
 412
 413         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 414         for (i = 0; i < 4; i++) {
 415                 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
 416         }
 417
 418         for (i = 0; i < 4; i++) {
 419                 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
 420         }
 421
 422         for (i = 0; i < OPENPIC_TIMERS; i++) {
 423                 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
 424                 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
 425                 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
 426                 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
 427         }
 428
 429         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 430                 sc->sc_saved_vectors[i] =
 431                     bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
 432
 433         return (0);
 434 }
 435
 436 int
 437 openpic_resume(device_t dev)
 438 {
 439         struct openpic_softc *sc;
 440         int i;
 441
 442         sc = device_get_softc(dev);
 443
 444         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 445         for (i = 0; i < 4; i++) {
 446                 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
 447         }
 448
 449         for (i = 0; i < 4; i++) {
 450                 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
 451         }
 452
 453         for (i = 0; i < OPENPIC_TIMERS; i++) {
 454                 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
 455                 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
 456                 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
 457                 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
 458         }
 459
 460         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 461                 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);
 462
 463         return (0);
 464 }