2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2002 Benno Rice.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
38 #include <sys/sched.h>
41 #include <machine/bus.h>
42 #include <machine/intr_machdep.h>
43 #include <machine/md_var.h>
44 #include <machine/pio.h>
45 #include <machine/resource.h>
50 #include <machine/openpicreg.h>
51 #include <machine/openpicvar.h>
55 devclass_t openpic_devclass;
60 static int openpic_intr(void *arg);
62 static __inline uint32_t
63 openpic_read(struct openpic_softc *sc, u_int reg)
65 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
69 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
71 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
75 openpic_set_priority(struct openpic_softc *sc, int pri)
81 tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
82 x = openpic_read(sc, tpr);
83 x &= ~OPENPIC_TPR_MASK;
85 openpic_write(sc, tpr, x);
90 openpic_common_attach(device_t dev, uint32_t node)
92 struct openpic_softc *sc;
96 sc = device_get_softc(dev);
100 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
103 if (sc->sc_memr == NULL) {
104 device_printf(dev, "Could not alloc mem resource!\n");
108 sc->sc_bt = rman_get_bustag(sc->sc_memr);
109 sc->sc_bh = rman_get_bushandle(sc->sc_memr);
112 x = openpic_read(sc, OPENPIC_CONFIG);
113 x |= OPENPIC_CONFIG_RESET;
114 openpic_write(sc, OPENPIC_CONFIG, x);
116 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
121 /* Check if this is a cascaded PIC */
125 struct resource_list *rl;
127 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
130 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
133 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
134 &sc->sc_irq, RF_ACTIVE);
136 /* XXX Cascaded PICs pass NULL trapframes! */
137 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
138 openpic_intr, NULL, dev, &sc->sc_icookie);
142 x = openpic_read(sc, OPENPIC_CONFIG);
143 x |= OPENPIC_CONFIG_RESET;
144 openpic_write(sc, OPENPIC_CONFIG, x);
146 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
151 x = openpic_read(sc, OPENPIC_FEATURE);
152 switch (x & OPENPIC_FEATURE_VERSION_MASK) {
154 sc->sc_version = "1.0";
157 sc->sc_version = "1.2";
160 sc->sc_version = "1.3";
163 sc->sc_version = "unknown";
167 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
168 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
169 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
170 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
173 * PSIM seems to report 1 too many IRQs and CPUs
182 "Version %s, supports %d CPUs and %d irqs\n",
183 sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
185 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
186 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
188 /* Reset and disable all interrupts. */
189 for (irq = 0; irq < sc->sc_nirq; irq++) {
190 x = irq; /* irq == vector. */
192 x |= OPENPIC_POLARITY_NEGATIVE;
193 x |= OPENPIC_SENSE_LEVEL;
194 x |= 8 << OPENPIC_PRIORITY_SHIFT;
195 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
198 /* Reset and disable all IPIs. */
199 for (ipi = 0; ipi < 4; ipi++) {
200 x = sc->sc_nirq + ipi;
202 x |= 15 << OPENPIC_PRIORITY_SHIFT;
203 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
206 /* we don't need 8259 passthrough mode */
207 x = openpic_read(sc, OPENPIC_CONFIG);
208 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
209 openpic_write(sc, OPENPIC_CONFIG, x);
211 /* send all interrupts to cpu 0 */
212 for (irq = 0; irq < sc->sc_nirq; irq++)
213 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
215 /* clear all pending interrupts from cpu 0 */
216 for (irq = 0; irq < sc->sc_nirq; irq++) {
217 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
218 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
221 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
222 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
224 powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
226 /* If this is not a cascaded PIC, it must be the root PIC */
227 if (sc->sc_intr == NULL)
238 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
240 struct openpic_softc *sc;
243 /* If we aren't directly connected to the CPU, this won't work */
247 sc = device_get_softc(dev);
250 * XXX: openpic_write() is very special and just needs a 32 bits mask.
251 * For the moment, just play dirty and get the first half word.
253 mask = cpumask.__bits[0] & 0xffffffff;
254 if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
255 int i = mftb() % CPU_COUNT(&cpumask);
260 if (!(mask & (1 << cpu)))
269 openpic_write(sc, OPENPIC_IDEST(irq), mask);
273 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
274 enum intr_polarity pol)
276 struct openpic_softc *sc;
279 sc = device_get_softc(dev);
280 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
281 if (pol == INTR_POLARITY_LOW)
282 x &= ~OPENPIC_POLARITY_POSITIVE;
284 x |= OPENPIC_POLARITY_POSITIVE;
285 if (trig == INTR_TRIGGER_EDGE)
286 x &= ~OPENPIC_SENSE_LEVEL;
288 x |= OPENPIC_SENSE_LEVEL;
289 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
293 openpic_intr(void *arg)
295 device_t dev = (device_t)(arg);
297 /* XXX Cascaded PICs do not pass non-NULL trapframes! */
298 openpic_dispatch(dev, NULL);
300 return (FILTER_HANDLED);
304 openpic_dispatch(device_t dev, struct trapframe *tf)
306 struct openpic_softc *sc;
309 CTR1(KTR_INTR, "%s: got interrupt", __func__);
311 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
313 sc = device_get_softc(dev);
315 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
316 vector &= OPENPIC_VECTOR_MASK;
319 powerpc_dispatch_intr(vector, tf);
324 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
326 struct openpic_softc *sc;
329 sc = device_get_softc(dev);
330 if (irq < sc->sc_nirq) {
331 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
332 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
334 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
336 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
337 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
339 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
344 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
346 struct openpic_softc *sc;
349 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
351 sc = device_get_softc(dev);
352 openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
356 openpic_ipi(device_t dev, u_int cpu)
358 struct openpic_softc *sc;
360 KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
362 sc = device_get_softc(dev);
364 openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
370 openpic_mask(device_t dev, u_int irq, void *priv __unused)
372 struct openpic_softc *sc;
375 sc = device_get_softc(dev);
376 if (irq < sc->sc_nirq) {
377 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
379 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
381 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
383 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
388 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
390 struct openpic_softc *sc;
393 sc = device_get_softc(dev);
394 if (irq < sc->sc_nirq) {
395 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
397 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
399 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
401 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
406 openpic_suspend(device_t dev)
408 struct openpic_softc *sc;
411 sc = device_get_softc(dev);
413 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
414 for (i = 0; i < 4; i++) {
415 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
418 for (i = 0; i < 4; i++) {
419 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
422 for (i = 0; i < OPENPIC_TIMERS; i++) {
423 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
424 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
425 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
426 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
429 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
430 sc->sc_saved_vectors[i] =
431 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
437 openpic_resume(device_t dev)
439 struct openpic_softc *sc;
442 sc = device_get_softc(dev);
444 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
445 for (i = 0; i < 4; i++) {
446 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
449 for (i = 0; i < 4; i++) {
450 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
453 for (i = 0; i < OPENPIC_TIMERS; i++) {
454 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
455 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
456 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
457 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
460 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
461 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);