sys/powerpc/powerpc/openpic.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2002 Benno Rice.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  21  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  22  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  23  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  24  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  25  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/conf.h>
  34 #include <sys/kernel.h>
  35 #include <sys/proc.h>
  36 #include <sys/rman.h>
  37 #include <sys/sched.h>
  38 #include <sys/smp.h>
  39
  40 #include <machine/bus.h>
  41 #include <machine/intr_machdep.h>
  42 #include <machine/md_var.h>
  43 #include <machine/pio.h>
  44 #include <machine/resource.h>
  45
  46 #include <vm/vm.h>
  47 #include <vm/pmap.h>
  48
  49 #include <machine/openpicreg.h>
  50 #include <machine/openpicvar.h>
  51
  52 #include "pic_if.h"
  53
  54 devclass_t openpic_devclass;
  55
  56 /*
  57  * Local routines
  58  */
  59 static int openpic_intr(void *arg);
  60
  61 static __inline uint32_t
  62 openpic_read(struct openpic_softc *sc, u_int reg)
  63 {
  64         return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
  65 }
  66
  67 static __inline void
  68 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
  69 {
  70         bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
  71 }
  72
  73 static __inline void
  74 openpic_set_priority(struct openpic_softc *sc, int pri)
  75 {
  76         u_int tpr;
  77         uint32_t x;
  78
  79         sched_pin();
  80         tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
  81         x = openpic_read(sc, tpr);
  82         x &= ~OPENPIC_TPR_MASK;
  83         x |= pri;
  84         openpic_write(sc, tpr, x);
  85         sched_unpin();
  86 }
  87
  88 int
  89 openpic_common_attach(device_t dev, uint32_t node)
  90 {
  91         struct openpic_softc *sc;
  92         u_int     cpu, ipi, irq;
  93         u_int32_t x;
  94
  95         sc = device_get_softc(dev);
  96         sc->sc_dev = dev;
  97
  98         sc->sc_rid = 0;
  99         sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
 100             RF_ACTIVE);
 101
 102         if (sc->sc_memr == NULL) {
 103                 device_printf(dev, "Could not alloc mem resource!\n");
 104                 return (ENXIO);
 105         }
 106
 107         sc->sc_bt = rman_get_bustag(sc->sc_memr);
 108         sc->sc_bh = rman_get_bushandle(sc->sc_memr);
 109
 110         /* Reset the PIC */
 111         x = openpic_read(sc, OPENPIC_CONFIG);
 112         x |= OPENPIC_CONFIG_RESET;
 113         openpic_write(sc, OPENPIC_CONFIG, x);
 114
 115         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 116                 powerpc_sync();
 117                 DELAY(100);
 118         }
 119
 120         /* Check if this is a cascaded PIC */
 121         sc->sc_irq = 0;
 122         sc->sc_intr = NULL;
 123         do {
 124                 struct resource_list *rl;
 125
 126                 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
 127                 if (rl == NULL)
 128                         break;
 129                 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
 130                         break;
 131
 132                 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 133                     &sc->sc_irq, RF_ACTIVE);
 134
 135                 /* XXX Cascaded PICs pass NULL trapframes! */
 136                 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
 137                     openpic_intr, NULL, dev, &sc->sc_icookie);
 138         } while (0);
 139
 140         /* Reset the PIC */
 141         x = openpic_read(sc, OPENPIC_CONFIG);
 142         x |= OPENPIC_CONFIG_RESET;
 143         openpic_write(sc, OPENPIC_CONFIG, x);
 144
 145         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 146                 powerpc_sync();
 147                 DELAY(100);
 148         }
 149
 150         x = openpic_read(sc, OPENPIC_FEATURE);
 151         switch (x & OPENPIC_FEATURE_VERSION_MASK) {
 152         case 1:
 153                 sc->sc_version = "1.0";
 154                 break;
 155         case 2:
 156                 sc->sc_version = "1.2";
 157                 break;
 158         case 3:
 159                 sc->sc_version = "1.3";
 160                 break;
 161         default:
 162                 sc->sc_version = "unknown";
 163                 break;
 164         }
 165
 166         sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
 167             OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
 168         sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
 169             OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
 170
 171         /*
 172          * PSIM seems to report 1 too many IRQs and CPUs
 173          */
 174         if (sc->sc_psim) {
 175                 sc->sc_nirq--;
 176                 sc->sc_ncpu--;
 177         }
 178
 179         if (bootverbose)
 180                 device_printf(dev,
 181                     "Version %s, supports %d CPUs and %d irqs\n",
 182                     sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
 183
 184         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 185                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
 186
 187         /* Reset and disable all interrupts. */
 188         for (irq = 0; irq < sc->sc_nirq; irq++) {
 189                 x = irq;                /* irq == vector. */
 190                 x |= OPENPIC_IMASK;
 191                 x |= OPENPIC_POLARITY_NEGATIVE;
 192                 x |= OPENPIC_SENSE_LEVEL;
 193                 x |= 8 << OPENPIC_PRIORITY_SHIFT;
 194                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 195         }
 196
 197         /* Reset and disable all IPIs. */
 198         for (ipi = 0; ipi < 4; ipi++) {
 199                 x = sc->sc_nirq + ipi;
 200                 x |= OPENPIC_IMASK;
 201                 x |= 15 << OPENPIC_PRIORITY_SHIFT;
 202                 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
 203         }
 204
 205         /* we don't need 8259 passthrough mode */
 206         x = openpic_read(sc, OPENPIC_CONFIG);
 207         x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
 208         openpic_write(sc, OPENPIC_CONFIG, x);
 209
 210         /* send all interrupts to cpu 0 */
 211         for (irq = 0; irq < sc->sc_nirq; irq++)
 212                 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
 213
 214         /* clear all pending interrupts from cpu 0 */
 215         for (irq = 0; irq < sc->sc_nirq; irq++) {
 216                 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
 217                 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
 218         }
 219
 220         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 221                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
 222
 223         powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
 224
 225         /* If this is not a cascaded PIC, it must be the root PIC */
 226         if (sc->sc_intr == NULL)
 227                 root_pic = dev;
 228
 229         return (0);
 230 }
 231
 232 /*
 233  * PIC I/F methods
 234  */
 235
 236 void
 237 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
 238 {
 239         struct openpic_softc *sc;
 240         uint32_t mask;
 241
 242         /* If we aren't directly connected to the CPU, this won't work */
 243         if (dev != root_pic)
 244                 return;
 245
 246         sc = device_get_softc(dev);
 247
 248         /*
 249          * XXX: openpic_write() is very special and just needs a 32 bits mask.
 250          * For the moment, just play dirty and get the first half word.
 251          */
 252         mask = cpumask.__bits[0] & 0xffffffff;
 253         if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
 254                 int i = mftb() % CPU_COUNT(&cpumask);
 255                 int cpu, ncpu;
 256
 257                 ncpu = 0;
 258                 CPU_FOREACH(cpu) {
 259                         if (!(mask & (1 << cpu)))
 260                                 continue;
 261                         if (ncpu == i)
 262                                 break;
 263                         ncpu++;
 264                 }
 265                 mask &= (1 << cpu);
 266         }
 267
 268         openpic_write(sc, OPENPIC_IDEST(irq), mask);
 269 }
 270
 271 void
 272 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
 273     enum intr_polarity pol)
 274 {
 275         struct openpic_softc *sc;
 276         uint32_t x;
 277
 278         sc = device_get_softc(dev);
 279         x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 280         if (pol == INTR_POLARITY_LOW)
 281                 x &= ~OPENPIC_POLARITY_POSITIVE;
 282         else
 283                 x |= OPENPIC_POLARITY_POSITIVE;
 284         if (trig == INTR_TRIGGER_EDGE)
 285                 x &= ~OPENPIC_SENSE_LEVEL;
 286         else
 287                 x |= OPENPIC_SENSE_LEVEL;
 288         openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 289 }
 290
 291 static int
 292 openpic_intr(void *arg)
 293 {
 294         device_t dev = (device_t)(arg);
 295
 296         /* XXX Cascaded PICs do not pass non-NULL trapframes! */
 297         openpic_dispatch(dev, NULL);
 298
 299         return (FILTER_HANDLED);
 300 }
 301
 302 void
 303 openpic_dispatch(device_t dev, struct trapframe *tf)
 304 {
 305         struct openpic_softc *sc;
 306         u_int cpuid, vector;
 307
 308         CTR1(KTR_INTR, "%s: got interrupt", __func__);
 309
 310         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 311
 312         sc = device_get_softc(dev);
 313         while (1) {
 314                 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
 315                 vector &= OPENPIC_VECTOR_MASK;
 316                 if (vector == 255)
 317                         break;
 318                 powerpc_dispatch_intr(vector, tf);
 319         }
 320 }
 321
 322 void
 323 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
 324 {
 325         struct openpic_softc *sc;
 326         uint32_t x;
 327
 328         sc = device_get_softc(dev);
 329         if (irq < sc->sc_nirq) {
 330                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 331                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 332                 x |= vector;
 333                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 334         } else {
 335                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 336                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 337                 x |= vector;
 338                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 339         }
 340 }
 341
 342 void
 343 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
 344 {
 345         struct openpic_softc *sc;
 346         u_int cpuid;
 347
 348         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 349
 350         sc = device_get_softc(dev);
 351         openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
 352 }
 353
 354 void
 355 openpic_ipi(device_t dev, u_int cpu)
 356 {
 357         struct openpic_softc *sc;
 358
 359         KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
 360
 361         sc = device_get_softc(dev);
 362         sched_pin();
 363         openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
 364             1u << cpu);
 365         sched_unpin();
 366 }
 367
 368 void
 369 openpic_mask(device_t dev, u_int irq, void *priv __unused)
 370 {
 371         struct openpic_softc *sc;
 372         uint32_t x;
 373
 374         sc = device_get_softc(dev);
 375         if (irq < sc->sc_nirq) {
 376                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 377                 x |= OPENPIC_IMASK;
 378                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 379         } else {
 380                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 381                 x |= OPENPIC_IMASK;
 382                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 383         }
 384 }
 385
 386 void
 387 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
 388 {
 389         struct openpic_softc *sc;
 390         uint32_t x;
 391
 392         sc = device_get_softc(dev);
 393         if (irq < sc->sc_nirq) {
 394                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 395                 x &= ~OPENPIC_IMASK;
 396                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 397         } else {
 398                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 399                 x &= ~OPENPIC_IMASK;
 400                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 401         }
 402 }
 403
 404 int
 405 openpic_suspend(device_t dev)
 406 {
 407         struct openpic_softc *sc;
 408         int i;
 409
 410         sc = device_get_softc(dev);
 411
 412         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 413         for (i = 0; i < 4; i++) {
 414                 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
 415         }
 416
 417         for (i = 0; i < 4; i++) {
 418                 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
 419         }
 420
 421         for (i = 0; i < OPENPIC_TIMERS; i++) {
 422                 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
 423                 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
 424                 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
 425                 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
 426         }
 427
 428         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 429                 sc->sc_saved_vectors[i] =
 430                     bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
 431
 432         return (0);
 433 }
 434
 435 int
 436 openpic_resume(device_t dev)
 437 {
 438         struct openpic_softc *sc;
 439         int i;
 440
 441         sc = device_get_softc(dev);
 442
 443         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 444         for (i = 0; i < 4; i++) {
 445                 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
 446         }
 447
 448         for (i = 0; i < 4; i++) {
 449                 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
 450         }
 451
 452         for (i = 0; i < OPENPIC_TIMERS; i++) {
 453                 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
 454                 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
 455                 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
 456                 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
 457         }
 458
 459         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 460                 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);
 461
 462         return (0);
 463 }