2 * Copyright (C) 2002 Benno Rice.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include <sys/param.h>
29 #include <sys/systm.h>
32 #include <sys/kernel.h>
35 #include <sys/sched.h>
37 #include <machine/bus.h>
38 #include <machine/intr_machdep.h>
39 #include <machine/md_var.h>
40 #include <machine/pio.h>
41 #include <machine/resource.h>
46 #include <machine/openpicreg.h>
47 #include <machine/openpicvar.h>
51 devclass_t openpic_devclass;
56 static int openpic_intr(void *arg);
58 static __inline uint32_t
59 openpic_read(struct openpic_softc *sc, u_int reg)
61 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
65 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
67 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
71 openpic_set_priority(struct openpic_softc *sc, int pri)
77 tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
78 x = openpic_read(sc, tpr);
79 x &= ~OPENPIC_TPR_MASK;
81 openpic_write(sc, tpr, x);
86 openpic_common_attach(device_t dev, uint32_t node)
88 struct openpic_softc *sc;
92 sc = device_get_softc(dev);
96 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
99 if (sc->sc_memr == NULL) {
100 device_printf(dev, "Could not alloc mem resource!\n");
104 sc->sc_bt = rman_get_bustag(sc->sc_memr);
105 sc->sc_bh = rman_get_bushandle(sc->sc_memr);
108 x = openpic_read(sc, OPENPIC_CONFIG);
109 x |= OPENPIC_CONFIG_RESET;
110 openpic_write(sc, OPENPIC_CONFIG, x);
112 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
117 /* Check if this is a cascaded PIC */
121 struct resource_list *rl;
123 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
126 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
129 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
130 &sc->sc_irq, RF_ACTIVE);
132 /* XXX Cascaded PICs pass NULL trapframes! */
133 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
134 openpic_intr, NULL, dev, &sc->sc_icookie);
138 x = openpic_read(sc, OPENPIC_CONFIG);
139 x |= OPENPIC_CONFIG_RESET;
140 openpic_write(sc, OPENPIC_CONFIG, x);
142 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
147 x = openpic_read(sc, OPENPIC_FEATURE);
148 switch (x & OPENPIC_FEATURE_VERSION_MASK) {
150 sc->sc_version = "1.0";
153 sc->sc_version = "1.2";
156 sc->sc_version = "1.3";
159 sc->sc_version = "unknown";
163 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
164 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
165 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
166 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
169 * PSIM seems to report 1 too many IRQs and CPUs
178 "Version %s, supports %d CPUs and %d irqs\n",
179 sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
181 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
182 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
184 /* Reset and disable all interrupts. */
185 for (irq = 0; irq < sc->sc_nirq; irq++) {
186 x = irq; /* irq == vector. */
188 x |= OPENPIC_POLARITY_NEGATIVE;
189 x |= OPENPIC_SENSE_LEVEL;
190 x |= 8 << OPENPIC_PRIORITY_SHIFT;
191 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
194 /* Reset and disable all IPIs. */
195 for (ipi = 0; ipi < 4; ipi++) {
196 x = sc->sc_nirq + ipi;
198 x |= 15 << OPENPIC_PRIORITY_SHIFT;
199 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
202 /* we don't need 8259 passthrough mode */
203 x = openpic_read(sc, OPENPIC_CONFIG);
204 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
205 openpic_write(sc, OPENPIC_CONFIG, x);
207 /* send all interrupts to cpu 0 */
208 for (irq = 0; irq < sc->sc_nirq; irq++)
209 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
211 /* clear all pending interrupts from cpu 0 */
212 for (irq = 0; irq < sc->sc_nirq; irq++) {
213 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
214 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
217 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
218 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
220 powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
222 /* If this is not a cascaded PIC, it must be the root PIC */
223 if (sc->sc_intr == NULL)
234 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask)
236 struct openpic_softc *sc;
238 /* If we aren't directly connected to the CPU, this won't work */
242 sc = device_get_softc(dev);
245 * XXX: openpic_write() is very special and just needs a 32 bits mask.
246 * For the moment, just play dirty and get the first half word.
248 openpic_write(sc, OPENPIC_IDEST(irq), cpumask.__bits[0] & 0xffffffff);
252 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
253 enum intr_polarity pol)
255 struct openpic_softc *sc;
258 sc = device_get_softc(dev);
259 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
260 if (pol == INTR_POLARITY_LOW)
261 x &= ~OPENPIC_POLARITY_POSITIVE;
263 x |= OPENPIC_POLARITY_POSITIVE;
264 if (trig == INTR_TRIGGER_EDGE)
265 x &= ~OPENPIC_SENSE_LEVEL;
267 x |= OPENPIC_SENSE_LEVEL;
268 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
272 openpic_intr(void *arg)
274 device_t dev = (device_t)(arg);
276 /* XXX Cascaded PICs do not pass non-NULL trapframes! */
277 openpic_dispatch(dev, NULL);
279 return (FILTER_HANDLED);
283 openpic_dispatch(device_t dev, struct trapframe *tf)
285 struct openpic_softc *sc;
288 CTR1(KTR_INTR, "%s: got interrupt", __func__);
290 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
292 sc = device_get_softc(dev);
294 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
295 vector &= OPENPIC_VECTOR_MASK;
298 powerpc_dispatch_intr(vector, tf);
303 openpic_enable(device_t dev, u_int irq, u_int vector)
305 struct openpic_softc *sc;
308 sc = device_get_softc(dev);
309 if (irq < sc->sc_nirq) {
310 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
311 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
313 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
315 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
316 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
318 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
323 openpic_eoi(device_t dev, u_int irq __unused)
325 struct openpic_softc *sc;
328 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
330 sc = device_get_softc(dev);
331 openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
335 openpic_ipi(device_t dev, u_int cpu)
337 struct openpic_softc *sc;
339 KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
341 sc = device_get_softc(dev);
343 openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
349 openpic_mask(device_t dev, u_int irq)
351 struct openpic_softc *sc;
354 sc = device_get_softc(dev);
355 if (irq < sc->sc_nirq) {
356 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
358 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
360 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
362 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
367 openpic_unmask(device_t dev, u_int irq)
369 struct openpic_softc *sc;
372 sc = device_get_softc(dev);
373 if (irq < sc->sc_nirq) {
374 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
376 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
378 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
380 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
385 openpic_suspend(device_t dev)
387 struct openpic_softc *sc;
390 sc = device_get_softc(dev);
392 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
393 for (i = 0; i < 4; i++) {
394 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
397 for (i = 0; i < 4; i++) {
398 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
401 for (i = 0; i < OPENPIC_TIMERS; i++) {
402 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
403 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
404 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
405 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
408 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
409 sc->sc_saved_vectors[i] =
410 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
416 openpic_resume(device_t dev)
418 struct openpic_softc *sc;
421 sc = device_get_softc(dev);
423 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
424 for (i = 0; i < 4; i++) {
425 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
428 for (i = 0; i < 4; i++) {
429 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
432 for (i = 0; i < OPENPIC_TIMERS; i++) {
433 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
434 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
435 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
436 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
439 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
440 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);