2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2002 Benno Rice.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/param.h>
31 #include <sys/systm.h>
34 #include <sys/kernel.h>
38 #include <sys/sched.h>
41 #include <machine/bus.h>
42 #include <machine/intr_machdep.h>
43 #include <machine/md_var.h>
44 #include <machine/pio.h>
45 #include <machine/resource.h>
50 #include <machine/openpicreg.h>
51 #include <machine/openpicvar.h>
55 #define OPENPIC_NIPIS 4
57 devclass_t openpic_devclass;
62 static int openpic_intr(void *arg);
64 static __inline uint32_t
65 openpic_read(struct openpic_softc *sc, u_int reg)
67 return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
71 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
73 bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
77 openpic_set_priority(struct openpic_softc *sc, int pri)
83 tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
84 x = openpic_read(sc, tpr);
85 x &= ~OPENPIC_TPR_MASK;
87 openpic_write(sc, tpr, x);
92 openpic_common_attach(device_t dev, uint32_t node)
94 struct openpic_softc *sc;
98 sc = device_get_softc(dev);
102 sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
105 if (sc->sc_memr == NULL) {
106 device_printf(dev, "Could not alloc mem resource!\n");
110 sc->sc_bt = rman_get_bustag(sc->sc_memr);
111 sc->sc_bh = rman_get_bushandle(sc->sc_memr);
114 x = openpic_read(sc, OPENPIC_CONFIG);
115 x |= OPENPIC_CONFIG_RESET;
116 openpic_write(sc, OPENPIC_CONFIG, x);
118 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
123 /* Check if this is a cascaded PIC */
127 struct resource_list *rl;
129 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
132 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
135 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
136 &sc->sc_irq, RF_ACTIVE);
138 /* XXX Cascaded PICs pass NULL trapframes! */
139 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
140 openpic_intr, NULL, dev, &sc->sc_icookie);
144 x = openpic_read(sc, OPENPIC_CONFIG);
145 x |= OPENPIC_CONFIG_RESET;
146 openpic_write(sc, OPENPIC_CONFIG, x);
148 while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
153 x = openpic_read(sc, OPENPIC_FEATURE);
154 switch (x & OPENPIC_FEATURE_VERSION_MASK) {
156 sc->sc_version = "1.0";
159 sc->sc_version = "1.2";
162 sc->sc_version = "1.3";
165 sc->sc_version = "unknown";
169 sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
170 OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
171 sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
172 OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
175 * PSIM seems to report 1 too many IRQs and CPUs
184 "Version %s, supports %d CPUs and %d irqs\n",
185 sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
188 * Allow more IRQs than what the PIC says it handles. Some Freescale PICs
189 * have MSIs that show up above the PIC's self-described 196 IRQs
190 * (P5020 starts MSI IRQs at 224).
192 if (sc->sc_quirks & OPENPIC_QUIRK_HIDDEN_IRQS)
193 sc->sc_nirq = OPENPIC_IRQMAX - OPENPIC_NIPIS;
195 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
196 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
198 /* Reset and disable all interrupts. */
199 for (irq = 0; irq < sc->sc_nirq; irq++) {
200 x = irq; /* irq == vector. */
202 x |= OPENPIC_POLARITY_NEGATIVE;
203 x |= OPENPIC_SENSE_LEVEL;
204 x |= 8 << OPENPIC_PRIORITY_SHIFT;
205 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
208 /* Reset and disable all IPIs. */
209 for (ipi = 0; ipi < OPENPIC_NIPIS; ipi++) {
210 x = sc->sc_nirq + ipi;
212 x |= 15 << OPENPIC_PRIORITY_SHIFT;
213 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
216 /* we don't need 8259 passthrough mode */
217 x = openpic_read(sc, OPENPIC_CONFIG);
218 x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
219 openpic_write(sc, OPENPIC_CONFIG, x);
221 /* send all interrupts to cpu 0 */
222 for (irq = 0; irq < sc->sc_nirq; irq++)
223 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
225 /* clear all pending interrupts from cpu 0 */
226 for (irq = 0; irq < sc->sc_nirq; irq++) {
227 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
228 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
231 for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
232 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
234 powerpc_register_pic(dev, node, sc->sc_nirq, OPENPIC_NIPIS, FALSE);
236 /* If this is not a cascaded PIC, it must be the root PIC */
237 if (sc->sc_intr == NULL)
248 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
250 struct openpic_softc *sc;
253 /* If we aren't directly connected to the CPU, this won't work */
257 sc = device_get_softc(dev);
260 * XXX: openpic_write() is very special and just needs a 32 bits mask.
261 * For the moment, just play dirty and get the first half word.
263 mask = cpumask.__bits[0] & 0xffffffff;
264 if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
265 int i = mftb() % CPU_COUNT(&cpumask);
270 if (!(mask & (1 << cpu)))
279 openpic_write(sc, OPENPIC_IDEST(irq), mask);
283 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
284 enum intr_polarity pol)
286 struct openpic_softc *sc;
289 sc = device_get_softc(dev);
290 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
291 if (pol == INTR_POLARITY_LOW)
292 x &= ~OPENPIC_POLARITY_POSITIVE;
294 x |= OPENPIC_POLARITY_POSITIVE;
295 if (trig == INTR_TRIGGER_EDGE)
296 x &= ~OPENPIC_SENSE_LEVEL;
298 x |= OPENPIC_SENSE_LEVEL;
299 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
303 openpic_intr(void *arg)
305 device_t dev = (device_t)(arg);
307 /* XXX Cascaded PICs do not pass non-NULL trapframes! */
308 openpic_dispatch(dev, NULL);
310 return (FILTER_HANDLED);
314 openpic_dispatch(device_t dev, struct trapframe *tf)
316 struct openpic_softc *sc;
319 CTR1(KTR_INTR, "%s: got interrupt", __func__);
321 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
323 sc = device_get_softc(dev);
325 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
326 vector &= OPENPIC_VECTOR_MASK;
329 powerpc_dispatch_intr(vector, tf);
334 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
336 struct openpic_softc *sc;
339 sc = device_get_softc(dev);
340 if (irq < sc->sc_nirq) {
341 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
342 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
344 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
346 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
347 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
349 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
354 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
356 struct openpic_softc *sc;
359 cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
361 sc = device_get_softc(dev);
362 openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
366 openpic_ipi(device_t dev, u_int cpu)
368 struct openpic_softc *sc;
370 KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
372 sc = device_get_softc(dev);
374 openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
380 openpic_mask(device_t dev, u_int irq, void *priv __unused)
382 struct openpic_softc *sc;
385 sc = device_get_softc(dev);
386 if (irq < sc->sc_nirq) {
387 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
389 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
391 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
393 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
398 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
400 struct openpic_softc *sc;
403 sc = device_get_softc(dev);
404 if (irq < sc->sc_nirq) {
405 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
407 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
409 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
411 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
416 openpic_suspend(device_t dev)
418 struct openpic_softc *sc;
421 sc = device_get_softc(dev);
423 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
424 for (i = 0; i < OPENPIC_NIPIS; i++) {
425 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
428 for (i = 0; i < 4; i++) {
429 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
432 for (i = 0; i < OPENPIC_TIMERS; i++) {
433 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
434 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
435 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
436 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
439 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
440 sc->sc_saved_vectors[i] =
441 bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
447 openpic_resume(device_t dev)
449 struct openpic_softc *sc;
452 sc = device_get_softc(dev);
454 sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
455 for (i = 0; i < OPENPIC_NIPIS; i++) {
456 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
459 for (i = 0; i < 4; i++) {
460 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
463 for (i = 0; i < OPENPIC_TIMERS; i++) {
464 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
465 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
466 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
467 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
470 for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
471 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);