sys/powerpc/powerpc/openpic.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (C) 2002 Benno Rice.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
  17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  19  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  21  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  22  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  23  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  24  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  25  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29
  30 #include <sys/param.h>
  31 #include <sys/systm.h>
  32 #include <sys/bus.h>
  33 #include <sys/conf.h>
  34 #include <sys/kernel.h>
  35 #include <sys/ktr.h>
  36 #include <sys/proc.h>
  37 #include <sys/rman.h>
  38 #include <sys/sched.h>
  39 #include <sys/smp.h>
  40
  41 #include <machine/bus.h>
  42 #include <machine/intr_machdep.h>
  43 #include <machine/md_var.h>
  44 #include <machine/pio.h>
  45 #include <machine/resource.h>
  46
  47 #include <vm/vm.h>
  48 #include <vm/pmap.h>
  49
  50 #include <machine/openpicreg.h>
  51 #include <machine/openpicvar.h>
  52
  53 #include "pic_if.h"
  54
  55 #define OPENPIC_NIPIS           4
  56
  57 devclass_t openpic_devclass;
  58
  59 /*
  60  * Local routines
  61  */
  62 static int openpic_intr(void *arg);
  63
  64 static __inline uint32_t
  65 openpic_read(struct openpic_softc *sc, u_int reg)
  66 {
  67         return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
  68 }
  69
  70 static __inline void
  71 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
  72 {
  73         bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
  74 }
  75
  76 static __inline void
  77 openpic_set_priority(struct openpic_softc *sc, int pri)
  78 {
  79         u_int tpr;
  80         uint32_t x;
  81
  82         sched_pin();
  83         tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
  84         x = openpic_read(sc, tpr);
  85         x &= ~OPENPIC_TPR_MASK;
  86         x |= pri;
  87         openpic_write(sc, tpr, x);
  88         sched_unpin();
  89 }
  90
  91 int
  92 openpic_common_attach(device_t dev, uint32_t node)
  93 {
  94         struct openpic_softc *sc;
  95         u_int     cpu, ipi, irq;
  96         u_int32_t x;
  97
  98         sc = device_get_softc(dev);
  99         sc->sc_dev = dev;
 100
 101         sc->sc_rid = 0;
 102         sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
 103             RF_ACTIVE);
 104
 105         if (sc->sc_memr == NULL) {
 106                 device_printf(dev, "Could not alloc mem resource!\n");
 107                 return (ENXIO);
 108         }
 109
 110         sc->sc_bt = rman_get_bustag(sc->sc_memr);
 111         sc->sc_bh = rman_get_bushandle(sc->sc_memr);
 112
 113         /* Reset the PIC */
 114         x = openpic_read(sc, OPENPIC_CONFIG);
 115         x |= OPENPIC_CONFIG_RESET;
 116         openpic_write(sc, OPENPIC_CONFIG, x);
 117
 118         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 119                 powerpc_sync();
 120                 DELAY(100);
 121         }
 122
 123         /* Check if this is a cascaded PIC */
 124         sc->sc_irq = 0;
 125         sc->sc_intr = NULL;
 126         do {
 127                 struct resource_list *rl;
 128
 129                 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
 130                 if (rl == NULL)
 131                         break;
 132                 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
 133                         break;
 134
 135                 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 136                     &sc->sc_irq, RF_ACTIVE);
 137
 138                 /* XXX Cascaded PICs pass NULL trapframes! */
 139                 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
 140                     openpic_intr, NULL, dev, &sc->sc_icookie);
 141         } while (0);
 142
 143         /* Reset the PIC */
 144         x = openpic_read(sc, OPENPIC_CONFIG);
 145         x |= OPENPIC_CONFIG_RESET;
 146         openpic_write(sc, OPENPIC_CONFIG, x);
 147
 148         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
 149                 powerpc_sync();
 150                 DELAY(100);
 151         }
 152
 153         x = openpic_read(sc, OPENPIC_FEATURE);
 154         switch (x & OPENPIC_FEATURE_VERSION_MASK) {
 155         case 1:
 156                 sc->sc_version = "1.0";
 157                 break;
 158         case 2:
 159                 sc->sc_version = "1.2";
 160                 break;
 161         case 3:
 162                 sc->sc_version = "1.3";
 163                 break;
 164         default:
 165                 sc->sc_version = "unknown";
 166                 break;
 167         }
 168
 169         sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
 170             OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
 171         sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
 172             OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
 173
 174         /*
 175          * PSIM seems to report 1 too many IRQs and CPUs
 176          */
 177         if (sc->sc_psim) {
 178                 sc->sc_nirq--;
 179                 sc->sc_ncpu--;
 180         }
 181
 182         if (bootverbose)
 183                 device_printf(dev,
 184                     "Version %s, supports %d CPUs and %d irqs\n",
 185                     sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
 186
 187         /*
 188          * Allow more IRQs than what the PIC says it handles.  Some Freescale PICs
 189          * have MSIs that show up above the PIC's self-described 196 IRQs
 190          * (P5020 starts MSI IRQs at 224).
 191          */
 192         if (sc->sc_quirks & OPENPIC_QUIRK_HIDDEN_IRQS)
 193                 sc->sc_nirq = OPENPIC_IRQMAX - OPENPIC_NIPIS;
 194
 195         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 196                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
 197
 198         /* Reset and disable all interrupts. */
 199         for (irq = 0; irq < sc->sc_nirq; irq++) {
 200                 x = irq;                /* irq == vector. */
 201                 x |= OPENPIC_IMASK;
 202                 x |= OPENPIC_POLARITY_NEGATIVE;
 203                 x |= OPENPIC_SENSE_LEVEL;
 204                 x |= 8 << OPENPIC_PRIORITY_SHIFT;
 205                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 206         }
 207
 208         /* Reset and disable all IPIs. */
 209         for (ipi = 0; ipi < OPENPIC_NIPIS; ipi++) {
 210                 x = sc->sc_nirq + ipi;
 211                 x |= OPENPIC_IMASK;
 212                 x |= 15 << OPENPIC_PRIORITY_SHIFT;
 213                 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
 214         }
 215
 216         /* we don't need 8259 passthrough mode */
 217         x = openpic_read(sc, OPENPIC_CONFIG);
 218         x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
 219         openpic_write(sc, OPENPIC_CONFIG, x);
 220
 221         /* send all interrupts to cpu 0 */
 222         for (irq = 0; irq < sc->sc_nirq; irq++)
 223                 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
 224
 225         /* clear all pending interrupts from cpu 0 */
 226         for (irq = 0; irq < sc->sc_nirq; irq++) {
 227                 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
 228                 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
 229         }
 230
 231         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
 232                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
 233
 234         powerpc_register_pic(dev, node, sc->sc_nirq, OPENPIC_NIPIS, FALSE);
 235
 236         /* If this is not a cascaded PIC, it must be the root PIC */
 237         if (sc->sc_intr == NULL)
 238                 root_pic = dev;
 239
 240         return (0);
 241 }
 242
 243 /*
 244  * PIC I/F methods
 245  */
 246
 247 void
 248 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
 249 {
 250         struct openpic_softc *sc;
 251         uint32_t mask;
 252
 253         /* If we aren't directly connected to the CPU, this won't work */
 254         if (dev != root_pic)
 255                 return;
 256
 257         sc = device_get_softc(dev);
 258
 259         /*
 260          * XXX: openpic_write() is very special and just needs a 32 bits mask.
 261          * For the moment, just play dirty and get the first half word.
 262          */
 263         mask = cpumask.__bits[0] & 0xffffffff;
 264         if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
 265                 int i = mftb() % CPU_COUNT(&cpumask);
 266                 int cpu, ncpu;
 267
 268                 ncpu = 0;
 269                 CPU_FOREACH(cpu) {
 270                         if (!(mask & (1 << cpu)))
 271                                 continue;
 272                         if (ncpu == i)
 273                                 break;
 274                         ncpu++;
 275                 }
 276                 mask &= (1 << cpu);
 277         }
 278
 279         openpic_write(sc, OPENPIC_IDEST(irq), mask);
 280 }
 281
 282 void
 283 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
 284     enum intr_polarity pol)
 285 {
 286         struct openpic_softc *sc;
 287         uint32_t x;
 288
 289         sc = device_get_softc(dev);
 290         x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 291         if (pol == INTR_POLARITY_LOW)
 292                 x &= ~OPENPIC_POLARITY_POSITIVE;
 293         else
 294                 x |= OPENPIC_POLARITY_POSITIVE;
 295         if (trig == INTR_TRIGGER_EDGE)
 296                 x &= ~OPENPIC_SENSE_LEVEL;
 297         else
 298                 x |= OPENPIC_SENSE_LEVEL;
 299         openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 300 }
 301
 302 static int
 303 openpic_intr(void *arg)
 304 {
 305         device_t dev = (device_t)(arg);
 306
 307         /* XXX Cascaded PICs do not pass non-NULL trapframes! */
 308         openpic_dispatch(dev, NULL);
 309
 310         return (FILTER_HANDLED);
 311 }
 312
 313 void
 314 openpic_dispatch(device_t dev, struct trapframe *tf)
 315 {
 316         struct openpic_softc *sc;
 317         u_int cpuid, vector;
 318
 319         CTR1(KTR_INTR, "%s: got interrupt", __func__);
 320
 321         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 322
 323         sc = device_get_softc(dev);
 324         while (1) {
 325                 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
 326                 vector &= OPENPIC_VECTOR_MASK;
 327                 if (vector == 255)
 328                         break;
 329                 powerpc_dispatch_intr(vector, tf);
 330         }
 331 }
 332
 333 void
 334 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
 335 {
 336         struct openpic_softc *sc;
 337         uint32_t x;
 338
 339         sc = device_get_softc(dev);
 340         if (irq < sc->sc_nirq) {
 341                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 342                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 343                 x |= vector;
 344                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 345         } else {
 346                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 347                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
 348                 x |= vector;
 349                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 350         }
 351 }
 352
 353 void
 354 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
 355 {
 356         struct openpic_softc *sc;
 357         u_int cpuid;
 358
 359         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
 360
 361         sc = device_get_softc(dev);
 362         openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
 363 }
 364
 365 void
 366 openpic_ipi(device_t dev, u_int cpu)
 367 {
 368         struct openpic_softc *sc;
 369
 370         KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
 371
 372         sc = device_get_softc(dev);
 373         sched_pin();
 374         openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
 375             1u << cpu);
 376         sched_unpin();
 377 }
 378
 379 void
 380 openpic_mask(device_t dev, u_int irq, void *priv __unused)
 381 {
 382         struct openpic_softc *sc;
 383         uint32_t x;
 384
 385         sc = device_get_softc(dev);
 386         if (irq < sc->sc_nirq) {
 387                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 388                 x |= OPENPIC_IMASK;
 389                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 390         } else {
 391                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 392                 x |= OPENPIC_IMASK;
 393                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 394         }
 395 }
 396
 397 void
 398 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
 399 {
 400         struct openpic_softc *sc;
 401         uint32_t x;
 402
 403         sc = device_get_softc(dev);
 404         if (irq < sc->sc_nirq) {
 405                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
 406                 x &= ~OPENPIC_IMASK;
 407                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
 408         } else {
 409                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
 410                 x &= ~OPENPIC_IMASK;
 411                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
 412         }
 413 }
 414
 415 int
 416 openpic_suspend(device_t dev)
 417 {
 418         struct openpic_softc *sc;
 419         int i;
 420
 421         sc = device_get_softc(dev);
 422
 423         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 424         for (i = 0; i < OPENPIC_NIPIS; i++) {
 425                 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
 426         }
 427
 428         for (i = 0; i < 4; i++) {
 429                 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
 430         }
 431
 432         for (i = 0; i < OPENPIC_TIMERS; i++) {
 433                 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
 434                 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
 435                 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
 436                 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
 437         }
 438
 439         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 440                 sc->sc_saved_vectors[i] =
 441                     bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
 442
 443         return (0);
 444 }
 445
 446 int
 447 openpic_resume(device_t dev)
 448 {
 449         struct openpic_softc *sc;
 450         int i;
 451
 452         sc = device_get_softc(dev);
 453
 454         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
 455         for (i = 0; i < OPENPIC_NIPIS; i++) {
 456                 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
 457         }
 458
 459         for (i = 0; i < 4; i++) {
 460                 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
 461         }
 462
 463         for (i = 0; i < OPENPIC_TIMERS; i++) {
 464                 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
 465                 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
 466                 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
 467                 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
 468         }
 469
 470         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
 471                 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);
 472
 473         return (0);
 474 }