2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by TooLs GmbH.
17 * 4. The name of TooLs GmbH may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * $NetBSD: trap.c,v 1.58 2002/03/04 04:07:35 dbj Exp $
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
42 #include <sys/mutex.h>
43 #include <sys/pioctl.h>
44 #include <sys/ptrace.h>
45 #include <sys/reboot.h>
46 #include <sys/syscall.h>
47 #include <sys/sysent.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
51 #include <sys/signalvar.h>
52 #include <sys/vmmeter.h>
54 #include <security/audit/audit.h>
58 #include <vm/vm_extern.h>
59 #include <vm/vm_param.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_map.h>
62 #include <vm/vm_page.h>
64 #include <machine/_inttypes.h>
65 #include <machine/altivec.h>
66 #include <machine/cpu.h>
67 #include <machine/db_machdep.h>
68 #include <machine/fpu.h>
69 #include <machine/frame.h>
70 #include <machine/pcb.h>
71 #include <machine/psl.h>
72 #include <machine/slb.h>
73 #include <machine/spr.h>
74 #include <machine/sr.h>
75 #include <machine/trap.h>
77 /* Below matches setjmp.S */
78 #define FAULTBUF_LR 21
81 #define FAULTBUF_CR 22
82 #define FAULTBUF_R14 3
84 #define MOREARGS(sp) ((caddr_t)((uintptr_t)(sp) + \
85 sizeof(struct callframe) - 3*sizeof(register_t))) /* more args go here */
87 static void trap_fatal(struct trapframe *frame);
88 static void printtrap(u_int vector, struct trapframe *frame, int isfatal,
90 static bool trap_pfault(struct trapframe *frame, bool user, int *signo,
92 static int fix_unaligned(struct thread *td, struct trapframe *frame);
93 static int handle_onfault(struct trapframe *frame);
94 static void syscall(struct trapframe *frame);
96 #if defined(__powerpc64__) && defined(AIM)
97 static void normalize_inputs(void);
100 extern vm_offset_t __startkernel;
103 int db_trap_glue(struct trapframe *); /* Called from trap_subr.S */
106 struct powerpc_exception {
112 #include <sys/dtrace_bsd.h>
114 int (*dtrace_invop_jump_addr)(struct trapframe *);
117 static struct powerpc_exception powerpc_exceptions[] = {
118 { EXC_CRIT, "critical input" },
119 { EXC_RST, "system reset" },
120 { EXC_MCHK, "machine check" },
121 { EXC_DSI, "data storage interrupt" },
122 { EXC_DSE, "data segment exception" },
123 { EXC_ISI, "instruction storage interrupt" },
124 { EXC_ISE, "instruction segment exception" },
125 { EXC_EXI, "external interrupt" },
126 { EXC_ALI, "alignment" },
127 { EXC_PGM, "program" },
128 { EXC_HEA, "hypervisor emulation assistance" },
129 { EXC_FPU, "floating-point unavailable" },
130 { EXC_APU, "auxiliary proc unavailable" },
131 { EXC_DECR, "decrementer" },
132 { EXC_FIT, "fixed-interval timer" },
133 { EXC_WDOG, "watchdog timer" },
134 { EXC_SC, "system call" },
135 { EXC_TRC, "trace" },
136 { EXC_FPA, "floating-point assist" },
137 { EXC_DEBUG, "debug" },
138 { EXC_PERF, "performance monitoring" },
139 { EXC_VEC, "altivec unavailable" },
140 { EXC_VSX, "vsx unavailable" },
141 { EXC_FAC, "facility unavailable" },
142 { EXC_ITMISS, "instruction tlb miss" },
143 { EXC_DLMISS, "data load tlb miss" },
144 { EXC_DSMISS, "data store tlb miss" },
145 { EXC_BPT, "instruction breakpoint" },
146 { EXC_SMI, "system management" },
147 { EXC_VECAST_G4, "altivec assist" },
148 { EXC_THRM, "thermal management" },
149 { EXC_RUNMODETRC, "run mode/trace" },
150 { EXC_SOFT_PATCH, "soft patch exception" },
154 #define ESR_BITMASK \
156 "\040b0\037b1\036b2\035b3\034PIL\033PRR\032PTR\031FP" \
157 "\030ST\027b9\026DLK\025ILK\024b12\023b13\022BO\021PIE" \
158 "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23" \
159 "\010SPE\007EPID\006b26\005b27\004b28\003b29\002b30\001b31"
160 #define MCSR_BITMASK \
162 "\040MCP\037ICERR\036DCERR\035TLBPERR\034L2MMU_MHIT\033b5\032b6\031b7" \
163 "\030b8\027b9\026b10\025NMI\024MAV\023MEA\022b14\021IF" \
164 "\020LD\017ST\016LDG\015b19\014b20\013b21\012b22\011b23" \
165 "\010b24\007b25\006b26\005b27\004b28\003b29\002TLBSYNC\001BSL2_ERR"
166 #define MSSSR_BITMASK \
168 "\040b0\037b1\036b2\035b3\034b4\033b5\032b6\031b7" \
169 "\030b8\027b9\026b10\025b11\024b12\023L2TAG\022L2DAT\021L3TAG" \
170 "\020L3DAT\017APE\016DPE\015TEA\014b20\013b21\012b22\011b23" \
171 "\010b24\007b25\006b26\005b27\004b28\003b29\002b30\001b31"
175 trapname(u_int vector)
177 struct powerpc_exception *pe;
179 for (pe = powerpc_exceptions; pe->vector != EXC_LAST; pe++) {
180 if (pe->vector == vector)
188 frame_is_trap_inst(struct trapframe *frame)
191 return (frame->exc == EXC_PGM && frame->srr1 & EXC_PGM_TRAP);
193 return ((frame->cpu.booke.esr & ESR_PTR) != 0);
198 trap(struct trapframe *frame)
222 type = ucode = frame->exc;
224 user = frame->srr1 & PSL_PR;
226 CTR3(KTR_TRAP, "trap: %s type=%s (%s)", td->td_name,
227 trapname(type), user ? "user" : "kernel");
231 * A trap can occur while DTrace executes a probe. Before
232 * executing the probe, DTrace blocks re-scheduling and sets
233 * a flag in its per-cpu flags to indicate that it doesn't
234 * want to fault. On returning from the probe, the no-fault
235 * flag is cleared and finally re-scheduling is enabled.
237 * If the DTrace kernel module has registered a trap handler,
238 * call it and if it returns non-zero, assume that it has
239 * handled the trap and modified the trap frame so that this
240 * function can return normally.
242 if (dtrace_trap_func != NULL && (*dtrace_trap_func)(frame, type) != 0)
248 td->td_frame = frame;
249 if (td->td_cowgen != p->p_cowgen)
250 thread_cow_update(td);
252 /* User Mode Traps */
256 frame->srr1 &= ~PSL_SE;
261 #if defined(__powerpc64__) && defined(AIM)
264 if (handle_user_slb_spill(&p->p_vmspace->vm_pmap,
265 (type == EXC_ISE) ? frame->srr0 : frame->dar) != 0){
273 if (trap_pfault(frame, true, &sig, &ucode))
282 KASSERT((td->td_pcb->pcb_flags & PCB_FPU) != PCB_FPU,
283 ("FPU already enabled for thread"));
288 KASSERT((td->td_pcb->pcb_flags & PCB_VEC) != PCB_VEC,
289 ("Altivec already enabled for thread"));
294 KASSERT((td->td_pcb->pcb_flags & PCB_VSX) != PCB_VSX,
295 ("VSX already enabled for thread"));
296 if (!(td->td_pcb->pcb_flags & PCB_VEC))
298 if (td->td_pcb->pcb_flags & PCB_FPU)
300 td->td_pcb->pcb_flags |= PCB_VSX;
305 fscr = mfspr(SPR_FSCR);
306 switch (fscr & FSCR_IC_MASK) {
309 "Hardware Transactional Memory subsystem disabled");
314 td->td_pcb->pcb_flags |= PCB_CFSCR | PCB_CDSCR;
319 td->td_pcb->pcb_flags |= PCB_CFSCR;
326 td->td_pcb->pcb_flags |= PCB_CFSCR;
331 td->td_pcb->pcb_flags |= PCB_CFSCR;
340 mtspr(SPR_FSCR, fscr & ~FSCR_IC_MASK);
351 * We get a VPU assist exception for IEEE mode
352 * vector operations on denormalized floats.
353 * Emulating this is a giant pain, so for now,
354 * just switch off IEEE mode and treat them as
359 td->td_pcb->pcb_vec.vscr |= ALTIVEC_VSCR_NJ;
364 if (fix_unaligned(td, frame) != 0) {
372 case EXC_DEBUG: /* Single stepping */
373 mtspr(SPR_DBSR, mfspr(SPR_DBSR));
374 frame->srr1 &= ~PSL_DE;
375 frame->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
381 /* Identify the trap reason */
382 if (frame_is_trap_inst(frame)) {
384 inst = fuword32((const void *)frame->srr0);
385 if (inst == 0x0FFFDDDD &&
386 dtrace_pid_probe_ptr != NULL) {
387 (*dtrace_pid_probe_ptr)(frame);
394 sig = ppc_instr_emulate(frame, td);
396 if (frame->srr1 & EXC_PGM_PRIV)
398 else if (frame->srr1 & EXC_PGM_ILLEGAL)
400 } else if (sig == SIGFPE)
401 ucode = FPE_FLTINV; /* Punt for now, invalid operation. */
407 * Note that this may not be recoverable for the user
408 * process, depending on the type of machine check,
409 * but it at least prevents the kernel from dying.
415 #if defined(__powerpc64__) && defined(AIM)
418 * Point to the instruction that generated the exception to execute it again,
419 * and normalize the register values.
430 /* Kernel Mode Traps */
432 KASSERT(cold || td->td_ucred != NULL,
433 ("kernel trap doesn't have ucred"));
437 if (frame_is_trap_inst(frame)) {
438 if (*(uint32_t *)frame->srr0 == EXC_DTRACE) {
439 if (dtrace_invop_jump_addr != NULL) {
440 dtrace_invop_jump_addr(frame);
447 if (db_trap_glue(frame))
451 #if defined(__powerpc64__) && defined(AIM)
453 if (td->td_pcb->pcb_cpu.aim.usr_vsid != 0 &&
454 (frame->dar & SEGMENT_MASK) == USER_ADDR) {
455 __asm __volatile ("slbmte %0, %1" ::
456 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid),
463 if (trap_pfault(frame, false, NULL, NULL))
467 if (handle_onfault(frame))
477 if (p->p_sysent->sv_transtrap != NULL)
478 sig = (p->p_sysent->sv_transtrap)(sig, type);
479 ksiginfo_init_trap(&ksi);
481 ksi.ksi_code = (int) ucode; /* XXX, not POSIX */
482 ksi.ksi_addr = (void *)frame->srr0;
483 ksi.ksi_trapno = type;
484 trapsignal(td, &ksi);
491 trap_fatal(struct trapframe *frame)
497 printtrap(frame->exc, frame, 1, (frame->srr1 & PSL_PR));
499 if (debugger_on_trap) {
500 kdb_why = KDB_WHY_TRAP;
501 handled = kdb_trap(frame->exc, 0, frame);
502 kdb_why = KDB_WHY_UNSET;
507 panic("%s trap", trapname(frame->exc));
511 cpu_printtrap(u_int vector, struct trapframe *frame, int isfatal, int user)
520 printf(" dsisr = 0x%lx\n",
521 (u_long)frame->cpu.aim.dsisr);
526 printf(" msssr0 = 0x%b\n",
527 (int)mfspr(SPR_MSSSR0), MSSSR_BITMASK);
535 pa = mfspr(SPR_MCARU);
536 pa = (pa << 32) | (u_register_t)mfspr(SPR_MCAR);
537 printf(" mcsr = 0x%b\n",
538 (int)mfspr(SPR_MCSR), MCSR_BITMASK);
539 printf(" mcar = 0x%jx\n", (uintmax_t)pa);
541 printf(" esr = 0x%b\n",
542 (int)frame->cpu.booke.esr, ESR_BITMASK);
547 printtrap(u_int vector, struct trapframe *frame, int isfatal, int user)
551 printf("%s %s trap:\n", isfatal ? "fatal" : "handled",
552 user ? "user" : "kernel");
554 printf(" exception = 0x%x (%s)\n", vector, trapname(vector));
560 printf(" virtual address = 0x%" PRIxPTR "\n", frame->dar);
565 printf(" virtual address = 0x%" PRIxPTR "\n", frame->srr0);
570 cpu_printtrap(vector, frame, isfatal, user);
571 printf(" srr0 = 0x%" PRIxPTR " (0x%" PRIxPTR ")\n",
572 frame->srr0, frame->srr0 - (register_t)(__startkernel - KERNBASE));
573 printf(" srr1 = 0x%lx\n", (u_long)frame->srr1);
574 printf(" current msr = 0x%" PRIxPTR "\n", mfmsr());
575 printf(" lr = 0x%" PRIxPTR " (0x%" PRIxPTR ")\n",
576 frame->lr, frame->lr - (register_t)(__startkernel - KERNBASE));
577 printf(" frame = %p\n", frame);
578 printf(" curthread = %p\n", curthread);
579 if (curthread != NULL)
580 printf(" pid = %d, comm = %s\n",
581 curthread->td_proc->p_pid, curthread->td_name);
586 * Handles a fatal fault when we have onfault state to recover. Returns
587 * non-zero if there was onfault recovery state available.
590 handle_onfault(struct trapframe *frame)
596 fb = td->td_pcb->pcb_onfault;
598 frame->srr0 = (*fb)->_jb[FAULTBUF_LR];
599 frame->fixreg[1] = (*fb)->_jb[FAULTBUF_R1];
600 frame->fixreg[2] = (*fb)->_jb[FAULTBUF_R2];
601 frame->fixreg[3] = 1;
602 frame->cr = (*fb)->_jb[FAULTBUF_CR];
603 bcopy(&(*fb)->_jb[FAULTBUF_R14], &frame->fixreg[14],
604 18 * sizeof(register_t));
605 td->td_pcb->pcb_onfault = NULL; /* Returns twice, not thrice */
612 cpu_fetch_syscall_args(struct thread *td)
615 struct trapframe *frame;
616 struct syscall_args *sa;
622 frame = td->td_frame;
625 sa->code = frame->fixreg[0];
626 params = (caddr_t)(frame->fixreg + FIRSTARG);
629 if (sa->code == SYS_syscall) {
631 * code is first argument,
632 * followed by actual args.
634 sa->code = *(register_t *) params;
635 params += sizeof(register_t);
637 } else if (sa->code == SYS___syscall) {
639 * Like syscall, but code is a quad,
640 * so as to maintain quad alignment
641 * for the rest of the args.
643 if (SV_PROC_FLAG(p, SV_ILP32)) {
644 params += sizeof(register_t);
645 sa->code = *(register_t *) params;
646 params += sizeof(register_t);
649 sa->code = *(register_t *) params;
650 params += sizeof(register_t);
655 if (sa->code >= p->p_sysent->sv_size)
656 sa->callp = &p->p_sysent->sv_table[0];
658 sa->callp = &p->p_sysent->sv_table[sa->code];
660 sa->narg = sa->callp->sy_narg;
662 if (SV_PROC_FLAG(p, SV_ILP32)) {
663 argsz = sizeof(uint32_t);
665 for (i = 0; i < n; i++)
666 sa->args[i] = ((u_register_t *)(params))[i] &
669 argsz = sizeof(uint64_t);
671 for (i = 0; i < n; i++)
672 sa->args[i] = ((u_register_t *)(params))[i];
676 error = copyin(MOREARGS(frame->fixreg[1]), sa->args + n,
677 (sa->narg - n) * argsz);
682 if (SV_PROC_FLAG(p, SV_ILP32) && sa->narg > n) {
683 /* Expand the size of arguments copied from the stack */
685 for (i = sa->narg; i >= n; i--)
686 sa->args[i] = ((uint32_t *)(&sa->args[n]))[i-n];
691 td->td_retval[0] = 0;
692 td->td_retval[1] = frame->fixreg[FIRSTARG + 1];
697 #include "../../kern/subr_syscall.c"
700 syscall(struct trapframe *frame)
705 td->td_frame = frame;
707 #if defined(__powerpc64__) && defined(AIM)
709 * Speculatively restore last user SLB segment, which we know is
710 * invalid already, since we are likely to do copyin()/copyout().
712 if (td->td_pcb->pcb_cpu.aim.usr_vsid != 0)
713 __asm __volatile ("slbmte %0, %1; isync" ::
714 "r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
722 trap_pfault(struct trapframe *frame, bool user, int *signo, int *ucode)
733 if (frame->exc == EXC_ISI) {
735 ftype = VM_PROT_EXECUTE;
736 if (frame->srr1 & SRR1_ISI_PFAULT)
737 ftype |= VM_PROT_READ;
741 if (frame->cpu.booke.esr & ESR_ST)
743 if (frame->cpu.aim.dsisr & DSISR_STORE)
745 ftype = VM_PROT_WRITE;
747 ftype = VM_PROT_READ;
751 KASSERT(p->p_vmspace != NULL, ("trap_pfault: vmspace NULL"));
752 map = &p->p_vmspace->vm_map;
754 rv = pmap_decode_kernel_ptr(eva, &is_user, &eva);
759 map = &p->p_vmspace->vm_map;
764 /* Fault in the page. */
765 rv = vm_fault_trap(map, eva, ftype, VM_FAULT_NORMAL, signo, ucode);
767 * XXXDTRACE: add dtrace_doubletrap_func here?
770 if (rv == KERN_SUCCESS)
773 if (!user && handle_onfault(frame))
780 * For now, this only deals with the particular unaligned access case
781 * that gcc tends to generate. Eventually it should handle all of the
782 * possibilities that can happen on a 32-bit PowerPC in big-endian mode.
786 fix_unaligned(struct thread *td, struct trapframe *frame)
788 struct thread *fputhread;
796 indicator = (frame->cpu.booke.esr & (ESR_ST|ESR_SPE));
797 if (indicator & ESR_SPE) {
798 if (copyin((void *)frame->srr0, &inst, sizeof(inst)) != 0)
800 reg = EXC_ALI_INST_RST(inst);
801 fpr = (double *)td->td_pcb->pcb_vec.vr[reg];
802 fputhread = PCPU_GET(vecthread);
804 /* Juggle the SPE to ensure that we've initialized
805 * the registers, and that their current state is in
808 if (fputhread != td) {
815 if (!(indicator & ESR_ST)) {
816 if (copyin((void *)frame->dar, fpr,
817 sizeof(double)) != 0)
819 frame->fixreg[reg] = td->td_pcb->pcb_vec.vr[reg][1];
822 td->td_pcb->pcb_vec.vr[reg][1] = frame->fixreg[reg];
823 if (copyout(fpr, (void *)frame->dar,
824 sizeof(double)) != 0)
831 indicator = (frame->cpu.booke.esr & ESR_ST) ? EXC_ALI_STFD : EXC_ALI_LFD;
833 indicator = EXC_ALI_OPCODE_INDICATOR(frame->cpu.aim.dsisr);
840 if (copyin((void *)frame->srr0, &inst, sizeof(inst)) != 0)
842 reg = EXC_ALI_INST_RST(inst);
844 reg = EXC_ALI_RST(frame->cpu.aim.dsisr);
846 fpr = &td->td_pcb->pcb_fpu.fpr[reg].fpr;
847 fputhread = PCPU_GET(fputhread);
849 /* Juggle the FPU to ensure that we've initialized
850 * the FPRs, and that their current state is in
853 if (fputhread != td) {
860 if (indicator == EXC_ALI_LFD) {
861 if (copyin((void *)frame->dar, fpr,
862 sizeof(double)) != 0)
866 if (copyout(fpr, (void *)frame->dar,
867 sizeof(double)) != 0)
878 #if defined(__powerpc64__) && defined(AIM)
879 #define MSKNSHL(x, m, n) "(((" #x ") & " #m ") << " #n ")"
880 #define MSKNSHR(x, m, n) "(((" #x ") & " #m ") >> " #n ")"
882 /* xvcpsgndp instruction, built in opcode format.
883 * This can be changed to use mnemonic after a toolchain update.
885 #define XVCPSGNDP(xt, xa, xb) \
886 __asm __volatile(".long (" \
887 MSKNSHL(60, 0x3f, 26) " | " \
888 MSKNSHL(xt, 0x1f, 21) " | " \
889 MSKNSHL(xa, 0x1f, 16) " | " \
890 MSKNSHL(xb, 0x1f, 11) " | " \
891 MSKNSHL(240, 0xff, 3) " | " \
892 MSKNSHR(xa, 0x20, 3) " | " \
893 MSKNSHR(xa, 0x20, 4) " | " \
894 MSKNSHR(xa, 0x20, 5) ")")
896 /* Macros to normalize 1 or 10 VSX registers */
897 #define NORM(x) XVCPSGNDP(x, x, x)
899 NORM(x ## 0); NORM(x ## 1); NORM(x ## 2); NORM(x ## 3); NORM(x ## 4); \
900 NORM(x ## 5); NORM(x ## 6); NORM(x ## 7); NORM(x ## 8); NORM(x ## 9)
903 normalize_inputs(void)
909 mtmsr(msr | PSL_VSX);
911 NORM(0); NORM(1); NORM(2); NORM(3); NORM(4);
912 NORM(5); NORM(6); NORM(7); NORM(8); NORM(9);
913 NORM10(1); NORM10(2); NORM10(3); NORM10(4); NORM10(5);
914 NORM(60); NORM(61); NORM(62); NORM(63);
923 db_trap_glue(struct trapframe *frame)
926 if (!(frame->srr1 & PSL_PR)
927 && (frame->exc == EXC_TRC || frame->exc == EXC_RUNMODETRC
928 || frame_is_trap_inst(frame)
929 || frame->exc == EXC_BPT
930 || frame->exc == EXC_DEBUG
931 || frame->exc == EXC_DSI)) {
932 int type = frame->exc;
934 /* Ignore DTrace traps. */
935 if (*(uint32_t *)frame->srr0 == EXC_DTRACE)
937 if (frame_is_trap_inst(frame)) {
940 return (kdb_trap(type, 0, frame));