2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2010 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/sockio.h>
33 #include <sys/endian.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
38 #include <sys/mutex.h>
39 #include <sys/kernel.h>
40 #include <sys/socket.h>
47 #include <net/if_var.h>
48 #include <net/ethernet.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51 #include <net/if_dl.h>
53 #include <machine/pio.h>
54 #include <machine/bus.h>
55 #include <machine/platform.h>
56 #include <machine/resource.h>
61 #include "ps3-hvcall.h"
62 #include "if_glcreg.h"
64 static int glc_probe(device_t);
65 static int glc_attach(device_t);
66 static void glc_init(void *xsc);
67 static void glc_start(struct ifnet *ifp);
68 static int glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
69 static void glc_set_multicast(struct glc_softc *sc);
70 static int glc_add_rxbuf(struct glc_softc *sc, int idx);
71 static int glc_add_rxbuf_dma(struct glc_softc *sc, int idx);
72 static int glc_encap(struct glc_softc *sc, struct mbuf **m_head,
74 static int glc_intr_filter(void *xsc);
75 static void glc_intr(void *xsc);
76 static void glc_tick(void *xsc);
77 static void glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr);
78 static int glc_media_change(struct ifnet *ifp);
80 static MALLOC_DEFINE(M_GLC, "gelic", "PS3 GELIC ethernet");
82 static device_method_t glc_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_probe, glc_probe),
85 DEVMETHOD(device_attach, glc_attach),
89 static driver_t glc_driver = {
92 sizeof(struct glc_softc)
95 static devclass_t glc_devclass;
97 DRIVER_MODULE(glc, ps3bus, glc_driver, glc_devclass, 0, 0);
100 glc_probe(device_t dev)
103 if (ps3bus_get_bustype(dev) != PS3_BUSTYPE_SYSBUS ||
104 ps3bus_get_devtype(dev) != PS3_DEVTYPE_GELIC)
107 device_set_desc(dev, "Playstation 3 GELIC Network Controller");
108 return (BUS_PROBE_SPECIFIC);
112 glc_getphys(void *xaddr, bus_dma_segment_t *segs, int nsegs, int error)
117 *(bus_addr_t *)xaddr = segs[0].ds_addr;
121 glc_attach(device_t dev)
123 struct glc_softc *sc;
124 struct glc_txsoft *txs;
125 uint64_t mac64, val, junk;
128 sc = device_get_softc(dev);
130 sc->sc_bus = ps3bus_get_bus(dev);
131 sc->sc_dev = ps3bus_get_device(dev);
134 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
136 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
137 sc->next_txdma_slot = 0;
138 sc->bsy_txdma_slots = 0;
139 sc->sc_next_rxdma_slot = 0;
140 sc->first_used_txdma_slot = -1;
143 * Shut down existing tasks.
146 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
147 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0);
149 sc->sc_ifp = if_alloc(IFT_ETHER);
150 sc->sc_ifp->if_softc = sc;
153 * Get MAC address and VLAN id
156 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_MAC_ADDRESS,
157 0, 0, 0, &mac64, &junk);
158 memcpy(sc->sc_enaddr, &((uint8_t *)&mac64)[2], sizeof(sc->sc_enaddr));
159 sc->sc_tx_vlan = sc->sc_rx_vlan = -1;
160 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID,
161 GELIC_VLAN_TX_ETHERNET, 0, 0, &val, &junk);
163 sc->sc_tx_vlan = val;
164 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID,
165 GELIC_VLAN_RX_ETHERNET, 0, 0, &val, &junk);
167 sc->sc_rx_vlan = val;
170 * Set up interrupt handler
173 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqid,
175 if (sc->sc_irq == NULL) {
176 device_printf(dev, "Could not allocate IRQ!\n");
177 mtx_destroy(&sc->sc_mtx);
181 bus_setup_intr(dev, sc->sc_irq,
182 INTR_TYPE_NET | INTR_MPSAFE | INTR_ENTROPY,
183 glc_intr_filter, glc_intr, sc, &sc->sc_irqctx);
184 sc->sc_hwirq_status = (uint64_t *)contigmalloc(8, M_GLC, M_ZERO, 0,
185 BUS_SPACE_MAXADDR_32BIT, 8, PAGE_SIZE);
186 lv1_net_set_interrupt_status_indicator(sc->sc_bus, sc->sc_dev,
187 vtophys(sc->sc_hwirq_status), 0);
188 lv1_net_set_interrupt_mask(sc->sc_bus, sc->sc_dev,
189 GELIC_INT_RXDONE | GELIC_INT_RXFRAME | GELIC_INT_PHY |
190 GELIC_INT_TX_CHAIN_END, 0);
196 err = bus_dma_tag_create(bus_get_dma_tag(dev), 32, 0,
197 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
198 129*sizeof(struct glc_dmadesc), 1, 128*sizeof(struct glc_dmadesc),
199 0, NULL,NULL, &sc->sc_dmadesc_tag);
201 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_txdmadesc,
202 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
203 &sc->sc_txdmadesc_map);
204 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map,
205 sc->sc_txdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys,
206 &sc->sc_txdmadesc_phys, 0);
207 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_rxdmadesc,
208 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
209 &sc->sc_rxdmadesc_map);
210 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
211 sc->sc_rxdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys,
212 &sc->sc_rxdmadesc_phys, 0);
214 err = bus_dma_tag_create(bus_get_dma_tag(dev), 128, 0,
215 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
216 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL,
218 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
219 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
220 BUS_SPACE_MAXSIZE_32BIT, 16, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL,
223 /* init transmit descriptors */
224 STAILQ_INIT(&sc->sc_txfreeq);
225 STAILQ_INIT(&sc->sc_txdirtyq);
227 /* create TX DMA maps */
229 for (i = 0; i < GLC_MAX_TX_PACKETS; i++) {
230 txs = &sc->sc_txsoft[i];
231 txs->txs_mbuf = NULL;
232 err = bus_dmamap_create(sc->sc_txdma_tag, 0, &txs->txs_dmamap);
235 "unable to create TX DMA map %d, error = %d\n",
238 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
241 /* Create the receive buffer DMA maps. */
242 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) {
243 err = bus_dmamap_create(sc->sc_rxdma_tag, 0,
244 &sc->sc_rxsoft[i].rxs_dmamap);
247 "unable to create RX DMA map %d, error = %d\n",
250 sc->sc_rxsoft[i].rxs_mbuf = NULL;
254 * Attach to network stack
257 if_initname(sc->sc_ifp, device_get_name(dev), device_get_unit(dev));
258 sc->sc_ifp->if_mtu = ETHERMTU;
259 sc->sc_ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
260 sc->sc_ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
261 sc->sc_ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_RXCSUM;
262 sc->sc_ifp->if_capenable = IFCAP_HWCSUM | IFCAP_RXCSUM;
263 sc->sc_ifp->if_start = glc_start;
264 sc->sc_ifp->if_ioctl = glc_ioctl;
265 sc->sc_ifp->if_init = glc_init;
267 ifmedia_init(&sc->sc_media, IFM_IMASK, glc_media_change,
269 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL);
270 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
271 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL);
272 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
273 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
274 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
275 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
277 IFQ_SET_MAXLEN(&sc->sc_ifp->if_snd, GLC_MAX_TX_PACKETS);
278 sc->sc_ifp->if_snd.ifq_drv_maxlen = GLC_MAX_TX_PACKETS;
279 IFQ_SET_READY(&sc->sc_ifp->if_snd);
281 ether_ifattach(sc->sc_ifp, sc->sc_enaddr);
282 sc->sc_ifp->if_hwassist = 0;
286 mtx_destroy(&sc->sc_mtx);
292 glc_init_locked(struct glc_softc *sc)
295 struct glc_rxsoft *rxs;
296 struct glc_txsoft *txs;
298 mtx_assert(&sc->sc_mtx, MA_OWNED);
300 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
301 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0);
303 glc_set_multicast(sc);
305 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) {
306 rxs = &sc->sc_rxsoft[i];
307 rxs->rxs_desc_slot = i;
309 if (rxs->rxs_mbuf == NULL) {
310 glc_add_rxbuf(sc, i);
312 if (rxs->rxs_mbuf == NULL) {
313 rxs->rxs_desc_slot = -1;
318 glc_add_rxbuf_dma(sc, i);
319 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
320 BUS_DMASYNC_PREREAD);
323 /* Clear TX dirty queue */
324 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
325 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
326 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap);
328 if (txs->txs_mbuf != NULL) {
329 m_freem(txs->txs_mbuf);
330 txs->txs_mbuf = NULL;
333 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
335 sc->first_used_txdma_slot = -1;
336 sc->bsy_txdma_slots = 0;
338 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev,
339 sc->sc_rxsoft[0].rxs_desc, 0);
341 device_printf(sc->sc_self,
342 "lv1_net_start_rx_dma error: %d\n", error);
344 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING;
345 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
346 sc->sc_ifpflags = sc->sc_ifp->if_flags;
348 sc->sc_wdog_timer = 0;
349 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc);
355 struct glc_softc *sc = xsc;
357 mtx_assert(&sc->sc_mtx, MA_OWNED);
359 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
360 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0);
366 struct glc_softc *sc = xsc;
368 mtx_lock(&sc->sc_mtx);
370 mtx_unlock(&sc->sc_mtx);
376 struct glc_softc *sc = xsc;
378 mtx_assert(&sc->sc_mtx, MA_OWNED);
381 * XXX: Sometimes the RX queue gets stuck. Poke it periodically until
382 * we figure out why. This will fail harmlessly if the RX queue is
385 lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev,
386 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0);
388 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) {
389 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc);
394 device_printf(sc->sc_self, "device timeout\n");
400 glc_start_locked(struct ifnet *ifp)
402 struct glc_softc *sc = ifp->if_softc;
403 bus_addr_t first, pktdesc;
406 struct mbuf *mb_head;
408 mtx_assert(&sc->sc_mtx, MA_OWNED);
411 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
415 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
418 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
419 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
424 /* Check if the ring buffer is full */
425 if (sc->bsy_txdma_slots > 125) {
426 /* Put the packet back and stop */
427 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
428 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
432 BPF_MTAP(ifp, mb_head);
434 if (sc->sc_tx_vlan >= 0)
435 mb_head = ether_vlanencap(mb_head, sc->sc_tx_vlan);
437 if (glc_encap(sc, &mb_head, &pktdesc)) {
438 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
446 if (kickstart && first != 0) {
447 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, first, 0);
449 device_printf(sc->sc_self,
450 "lv1_net_start_tx_dma error: %d\n", error);
451 sc->sc_wdog_timer = 5;
456 glc_start(struct ifnet *ifp)
458 struct glc_softc *sc = ifp->if_softc;
460 mtx_lock(&sc->sc_mtx);
461 glc_start_locked(ifp);
462 mtx_unlock(&sc->sc_mtx);
466 glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
468 struct glc_softc *sc = ifp->if_softc;
469 struct ifreq *ifr = (struct ifreq *)data;
474 mtx_lock(&sc->sc_mtx);
475 if ((ifp->if_flags & IFF_UP) != 0) {
476 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
477 ((ifp->if_flags ^ sc->sc_ifpflags) &
478 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
479 glc_set_multicast(sc);
483 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
485 sc->sc_ifpflags = ifp->if_flags;
486 mtx_unlock(&sc->sc_mtx);
490 mtx_lock(&sc->sc_mtx);
491 glc_set_multicast(sc);
492 mtx_unlock(&sc->sc_mtx);
496 err = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
499 err = ether_ioctl(ifp, cmd, data);
507 glc_add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
509 struct glc_softc *sc = arg;
513 * Filter can only hold 32 addresses, so fall back to
514 * the IFF_ALLMULTI case if we have too many. +1 is for
521 memcpy(&((uint8_t *)(&addr))[2], LLADDR(sdl), ETHER_ADDR_LEN);
522 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, addr, 0);
528 glc_set_multicast(struct glc_softc *sc)
530 struct ifnet *ifp = sc->sc_ifp;
533 /* Clear multicast filter */
534 lv1_net_remove_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1);
537 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev,
540 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
541 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1);
543 naddrs = if_foreach_llmaddr(ifp, glc_add_maddr, sc);
544 if (naddrs + 1 == 32)
545 lv1_net_add_multicast_address(sc->sc_bus,
551 glc_add_rxbuf(struct glc_softc *sc, int idx)
553 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx];
555 bus_dma_segment_t segs[1];
558 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
561 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
563 if (rxs->rxs_mbuf != NULL) {
564 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap,
565 BUS_DMASYNC_POSTREAD);
566 bus_dmamap_unload(sc->sc_rxdma_tag, rxs->rxs_dmamap);
569 error = bus_dmamap_load_mbuf_sg(sc->sc_rxdma_tag, rxs->rxs_dmamap, m,
570 segs, &nsegs, BUS_DMA_NOWAIT);
572 device_printf(sc->sc_self,
573 "cannot load RS DMA map %d, error = %d\n", idx, error);
577 /* If nsegs is wrong then the stack is corrupt. */
579 ("%s: too many DMA segments (%d)", __func__, nsegs));
581 rxs->segment = segs[0];
583 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
589 glc_add_rxbuf_dma(struct glc_softc *sc, int idx)
591 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx];
593 bzero(&sc->sc_rxdmadesc[idx], sizeof(sc->sc_rxdmadesc[idx]));
594 sc->sc_rxdmadesc[idx].paddr = rxs->segment.ds_addr;
595 sc->sc_rxdmadesc[idx].len = rxs->segment.ds_len;
596 sc->sc_rxdmadesc[idx].next = sc->sc_rxdmadesc_phys +
597 ((idx + 1) % GLC_MAX_RX_PACKETS)*sizeof(sc->sc_rxdmadesc[idx]);
598 sc->sc_rxdmadesc[idx].cmd_stat = GELIC_DESCR_OWNED;
600 rxs->rxs_desc_slot = idx;
601 rxs->rxs_desc = sc->sc_rxdmadesc_phys + idx*sizeof(struct glc_dmadesc);
607 glc_encap(struct glc_softc *sc, struct mbuf **m_head, bus_addr_t *pktdesc)
609 bus_dma_segment_t segs[16];
610 struct glc_txsoft *txs;
612 bus_addr_t firstslotphys;
613 int i, idx, nsegs, nsegs_max;
616 /* Max number of segments is the number of free DMA slots */
617 nsegs_max = 128 - sc->bsy_txdma_slots;
619 if (nsegs_max > 16 || sc->first_used_txdma_slot < 0)
622 /* Get a work queue entry. */
623 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
624 /* Ran out of descriptors. */
629 for (m = *m_head; m != NULL; m = m->m_next)
632 if (nsegs > nsegs_max) {
633 m = m_collapse(*m_head, M_NOWAIT, nsegs_max);
642 err = bus_dmamap_load_mbuf_sg(sc->sc_txdma_tag, txs->txs_dmamap,
643 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
650 KASSERT(nsegs <= 128 - sc->bsy_txdma_slots,
651 ("GLC: Mapped too many (%d) DMA segments with %d available",
652 nsegs, 128 - sc->bsy_txdma_slots));
660 txs->txs_ndescs = nsegs;
661 txs->txs_firstdesc = sc->next_txdma_slot;
663 idx = txs->txs_firstdesc;
664 firstslotphys = sc->sc_txdmadesc_phys +
665 txs->txs_firstdesc*sizeof(struct glc_dmadesc);
667 for (i = 0; i < nsegs; i++) {
668 bzero(&sc->sc_txdmadesc[idx], sizeof(sc->sc_txdmadesc[idx]));
669 sc->sc_txdmadesc[idx].paddr = segs[i].ds_addr;
670 sc->sc_txdmadesc[idx].len = segs[i].ds_len;
671 sc->sc_txdmadesc[idx].next = sc->sc_txdmadesc_phys +
672 ((idx + 1) % GLC_MAX_TX_PACKETS)*sizeof(struct glc_dmadesc);
673 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_NOIPSEC;
676 txs->txs_lastdesc = idx;
677 sc->sc_txdmadesc[idx].next = 0;
678 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_LAST;
681 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
682 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_TCP;
683 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
684 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_UDP;
685 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_DESCR_OWNED;
687 idx = (idx + 1) % GLC_MAX_TX_PACKETS;
689 sc->next_txdma_slot = idx;
690 sc->bsy_txdma_slots += nsegs;
691 if (txs->txs_firstdesc != 0)
692 idx = txs->txs_firstdesc - 1;
694 idx = GLC_MAX_TX_PACKETS - 1;
696 if (sc->first_used_txdma_slot < 0)
697 sc->first_used_txdma_slot = txs->txs_firstdesc;
699 bus_dmamap_sync(sc->sc_txdma_tag, txs->txs_dmamap,
700 BUS_DMASYNC_PREWRITE);
701 sc->sc_txdmadesc[idx].next = firstslotphys;
703 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
704 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
705 txs->txs_mbuf = *m_head;
706 *pktdesc = firstslotphys;
712 glc_rxintr(struct glc_softc *sc)
714 int i, restart_rxdma, error;
716 struct ifnet *ifp = sc->sc_ifp;
718 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
719 BUS_DMASYNC_POSTREAD);
722 while ((sc->sc_rxdmadesc[sc->sc_next_rxdma_slot].cmd_stat &
723 GELIC_DESCR_OWNED) == 0) {
724 i = sc->sc_next_rxdma_slot;
725 sc->sc_next_rxdma_slot++;
726 if (sc->sc_next_rxdma_slot >= GLC_MAX_RX_PACKETS)
727 sc->sc_next_rxdma_slot = 0;
729 if (sc->sc_rxdmadesc[i].cmd_stat & GELIC_CMDSTAT_CHAIN_END)
732 if (sc->sc_rxdmadesc[i].rxerror & GELIC_RXERRORS) {
733 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
737 m = sc->sc_rxsoft[i].rxs_mbuf;
738 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_IPCSUM) {
739 m->m_pkthdr.csum_flags |=
740 CSUM_IP_CHECKED | CSUM_IP_VALID;
742 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_TCPUDPCSUM) {
743 m->m_pkthdr.csum_flags |=
744 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
745 m->m_pkthdr.csum_data = 0xffff;
748 if (glc_add_rxbuf(sc, i)) {
749 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
753 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
754 m->m_pkthdr.rcvif = ifp;
755 m->m_len = sc->sc_rxdmadesc[i].valid_size;
756 m->m_pkthdr.len = m->m_len;
759 * Remove VLAN tag. Even on early firmwares that do not allow
760 * multiple VLANs, the VLAN tag is still in place here.
764 mtx_unlock(&sc->sc_mtx);
765 (*ifp->if_input)(ifp, m);
766 mtx_lock(&sc->sc_mtx);
769 glc_add_rxbuf_dma(sc, i);
772 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
773 BUS_DMASYNC_PREWRITE);
776 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev,
777 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0);
779 device_printf(sc->sc_self,
780 "lv1_net_start_rx_dma error: %d\n", error);
785 glc_txintr(struct glc_softc *sc)
787 struct ifnet *ifp = sc->sc_ifp;
788 struct glc_txsoft *txs;
789 int progress = 0, kickstart = 0, error;
791 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map,
792 BUS_DMASYNC_POSTREAD);
794 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
795 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat
799 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
800 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap);
801 sc->bsy_txdma_slots -= txs->txs_ndescs;
803 if (txs->txs_mbuf != NULL) {
804 m_freem(txs->txs_mbuf);
805 txs->txs_mbuf = NULL;
808 if ((sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 0xf0000000)
810 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
812 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
815 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat &
816 GELIC_CMDSTAT_CHAIN_END)
819 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
820 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
825 sc->first_used_txdma_slot = txs->txs_firstdesc;
827 sc->first_used_txdma_slot = -1;
829 if (kickstart || txs != NULL) {
830 /* Speculatively (or necessarily) start the TX queue again */
831 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev,
832 sc->sc_txdmadesc_phys +
833 ((txs == NULL) ? 0 : txs->txs_firstdesc)*
834 sizeof(struct glc_dmadesc), 0);
836 device_printf(sc->sc_self,
837 "lv1_net_start_tx_dma error: %d\n", error);
842 * We freed some descriptors, so reset IFF_DRV_OACTIVE
845 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
846 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
848 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
849 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
850 glc_start_locked(ifp);
855 glc_intr_filter(void *xsc)
857 struct glc_softc *sc = xsc;
860 atomic_set_64(&sc->sc_interrupt_status, *sc->sc_hwirq_status);
861 return (FILTER_SCHEDULE_THREAD);
867 struct glc_softc *sc = xsc;
868 uint64_t status, linkstat, junk;
870 mtx_lock(&sc->sc_mtx);
872 status = atomic_readandclear_64(&sc->sc_interrupt_status);
875 mtx_unlock(&sc->sc_mtx);
879 if (status & (GELIC_INT_RXDONE | GELIC_INT_RXFRAME))
882 if (status & (GELIC_INT_TXDONE | GELIC_INT_TX_CHAIN_END))
885 if (status & GELIC_INT_PHY) {
886 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS,
887 GELIC_VLAN_TX_ETHERNET, 0, 0, &linkstat, &junk);
889 linkstat = (linkstat & GELIC_LINK_UP) ?
890 LINK_STATE_UP : LINK_STATE_DOWN;
891 if (linkstat != sc->sc_ifp->if_link_state)
892 if_link_state_change(sc->sc_ifp, linkstat);
895 mtx_unlock(&sc->sc_mtx);
899 glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
901 struct glc_softc *sc = ifp->if_softc;
902 uint64_t status, junk;
904 ifmr->ifm_status = IFM_AVALID;
905 ifmr->ifm_active = IFM_ETHER;
907 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS,
908 GELIC_VLAN_TX_ETHERNET, 0, 0, &status, &junk);
910 if (status & GELIC_LINK_UP)
911 ifmr->ifm_status |= IFM_ACTIVE;
913 if (status & GELIC_SPEED_10)
914 ifmr->ifm_active |= IFM_10_T;
915 else if (status & GELIC_SPEED_100)
916 ifmr->ifm_active |= IFM_100_TX;
917 else if (status & GELIC_SPEED_1000)
918 ifmr->ifm_active |= IFM_1000_T;
920 if (status & GELIC_FULL_DUPLEX)
921 ifmr->ifm_active |= IFM_FDX;
923 ifmr->ifm_active |= IFM_HDX;
927 glc_media_change(struct ifnet *ifp)
929 struct glc_softc *sc = ifp->if_softc;
933 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
936 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) {
938 mode = GELIC_AUTO_NEG;
941 mode = GELIC_SPEED_10;
944 mode = GELIC_SPEED_100;
947 mode = GELIC_SPEED_1000 | GELIC_FULL_DUPLEX;
953 if (IFM_OPTIONS(sc->sc_media.ifm_media) & IFM_FDX)
954 mode |= GELIC_FULL_DUPLEX;
956 result = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_SET_LINK_MODE,
957 GELIC_VLAN_TX_ETHERNET, mode, 0, &junk, &junk);
959 return (result ? EIO : 0);