2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2010 Nathan Whitehorn
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/sockio.h>
33 #include <sys/endian.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
38 #include <sys/mutex.h>
39 #include <sys/kernel.h>
40 #include <sys/socket.h>
47 #include <net/if_var.h>
48 #include <net/ethernet.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51 #include <net/if_dl.h>
53 #include <machine/pio.h>
54 #include <machine/bus.h>
55 #include <machine/platform.h>
56 #include <machine/resource.h>
61 #include "ps3-hvcall.h"
62 #include "if_glcreg.h"
64 static int glc_probe(device_t);
65 static int glc_attach(device_t);
66 static void glc_init(void *xsc);
67 static void glc_start(struct ifnet *ifp);
68 static int glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
69 static void glc_set_multicast(struct glc_softc *sc);
70 static int glc_add_rxbuf(struct glc_softc *sc, int idx);
71 static int glc_add_rxbuf_dma(struct glc_softc *sc, int idx);
72 static int glc_encap(struct glc_softc *sc, struct mbuf **m_head,
74 static int glc_intr_filter(void *xsc);
75 static void glc_intr(void *xsc);
76 static void glc_tick(void *xsc);
77 static void glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr);
78 static int glc_media_change(struct ifnet *ifp);
80 static MALLOC_DEFINE(M_GLC, "gelic", "PS3 GELIC ethernet");
82 static device_method_t glc_methods[] = {
83 /* Device interface */
84 DEVMETHOD(device_probe, glc_probe),
85 DEVMETHOD(device_attach, glc_attach),
90 static driver_t glc_driver = {
93 sizeof(struct glc_softc)
96 static devclass_t glc_devclass;
98 DRIVER_MODULE(glc, ps3bus, glc_driver, glc_devclass, 0, 0);
101 glc_probe(device_t dev)
104 if (ps3bus_get_bustype(dev) != PS3_BUSTYPE_SYSBUS ||
105 ps3bus_get_devtype(dev) != PS3_DEVTYPE_GELIC)
108 device_set_desc(dev, "Playstation 3 GELIC Network Controller");
109 return (BUS_PROBE_SPECIFIC);
113 glc_getphys(void *xaddr, bus_dma_segment_t *segs, int nsegs, int error)
118 *(bus_addr_t *)xaddr = segs[0].ds_addr;
122 glc_attach(device_t dev)
124 struct glc_softc *sc;
125 struct glc_txsoft *txs;
126 uint64_t mac64, val, junk;
129 sc = device_get_softc(dev);
131 sc->sc_bus = ps3bus_get_bus(dev);
132 sc->sc_dev = ps3bus_get_device(dev);
135 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
137 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
138 sc->next_txdma_slot = 0;
139 sc->bsy_txdma_slots = 0;
140 sc->sc_next_rxdma_slot = 0;
141 sc->first_used_txdma_slot = -1;
144 * Shut down existing tasks.
147 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
148 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0);
150 sc->sc_ifp = if_alloc(IFT_ETHER);
151 sc->sc_ifp->if_softc = sc;
154 * Get MAC address and VLAN id
157 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_MAC_ADDRESS,
158 0, 0, 0, &mac64, &junk);
159 memcpy(sc->sc_enaddr, &((uint8_t *)&mac64)[2], sizeof(sc->sc_enaddr));
160 sc->sc_tx_vlan = sc->sc_rx_vlan = -1;
161 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID,
162 GELIC_VLAN_TX_ETHERNET, 0, 0, &val, &junk);
164 sc->sc_tx_vlan = val;
165 err = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_VLAN_ID,
166 GELIC_VLAN_RX_ETHERNET, 0, 0, &val, &junk);
168 sc->sc_rx_vlan = val;
171 * Set up interrupt handler
174 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irqid,
176 if (sc->sc_irq == NULL) {
177 device_printf(dev, "Could not allocate IRQ!\n");
178 mtx_destroy(&sc->sc_mtx);
182 bus_setup_intr(dev, sc->sc_irq,
183 INTR_TYPE_NET | INTR_MPSAFE | INTR_ENTROPY,
184 glc_intr_filter, glc_intr, sc, &sc->sc_irqctx);
185 sc->sc_hwirq_status = (uint64_t *)contigmalloc(8, M_GLC, M_ZERO, 0,
186 BUS_SPACE_MAXADDR_32BIT, 8, PAGE_SIZE);
187 lv1_net_set_interrupt_status_indicator(sc->sc_bus, sc->sc_dev,
188 vtophys(sc->sc_hwirq_status), 0);
189 lv1_net_set_interrupt_mask(sc->sc_bus, sc->sc_dev,
190 GELIC_INT_RXDONE | GELIC_INT_RXFRAME | GELIC_INT_PHY |
191 GELIC_INT_TX_CHAIN_END, 0);
197 err = bus_dma_tag_create(bus_get_dma_tag(dev), 32, 0,
198 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
199 129*sizeof(struct glc_dmadesc), 1, 128*sizeof(struct glc_dmadesc),
200 0, NULL,NULL, &sc->sc_dmadesc_tag);
202 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_txdmadesc,
203 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
204 &sc->sc_txdmadesc_map);
205 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map,
206 sc->sc_txdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys,
207 &sc->sc_txdmadesc_phys, 0);
208 err = bus_dmamem_alloc(sc->sc_dmadesc_tag, (void **)&sc->sc_rxdmadesc,
209 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
210 &sc->sc_rxdmadesc_map);
211 err = bus_dmamap_load(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
212 sc->sc_rxdmadesc, 128*sizeof(struct glc_dmadesc), glc_getphys,
213 &sc->sc_rxdmadesc_phys, 0);
215 err = bus_dma_tag_create(bus_get_dma_tag(dev), 128, 0,
216 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
217 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL,
219 err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
220 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
221 BUS_SPACE_MAXSIZE_32BIT, 16, BUS_SPACE_MAXSIZE_32BIT, 0, NULL,NULL,
224 /* init transmit descriptors */
225 STAILQ_INIT(&sc->sc_txfreeq);
226 STAILQ_INIT(&sc->sc_txdirtyq);
228 /* create TX DMA maps */
230 for (i = 0; i < GLC_MAX_TX_PACKETS; i++) {
231 txs = &sc->sc_txsoft[i];
232 txs->txs_mbuf = NULL;
233 err = bus_dmamap_create(sc->sc_txdma_tag, 0, &txs->txs_dmamap);
236 "unable to create TX DMA map %d, error = %d\n",
239 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
242 /* Create the receive buffer DMA maps. */
243 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) {
244 err = bus_dmamap_create(sc->sc_rxdma_tag, 0,
245 &sc->sc_rxsoft[i].rxs_dmamap);
248 "unable to create RX DMA map %d, error = %d\n",
251 sc->sc_rxsoft[i].rxs_mbuf = NULL;
255 * Attach to network stack
258 if_initname(sc->sc_ifp, device_get_name(dev), device_get_unit(dev));
259 sc->sc_ifp->if_mtu = ETHERMTU;
260 sc->sc_ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
261 sc->sc_ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
262 sc->sc_ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_RXCSUM;
263 sc->sc_ifp->if_capenable = IFCAP_HWCSUM | IFCAP_RXCSUM;
264 sc->sc_ifp->if_start = glc_start;
265 sc->sc_ifp->if_ioctl = glc_ioctl;
266 sc->sc_ifp->if_init = glc_init;
268 ifmedia_init(&sc->sc_media, IFM_IMASK, glc_media_change,
270 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL);
271 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
272 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL);
273 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
274 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
275 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
276 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
278 IFQ_SET_MAXLEN(&sc->sc_ifp->if_snd, GLC_MAX_TX_PACKETS);
279 sc->sc_ifp->if_snd.ifq_drv_maxlen = GLC_MAX_TX_PACKETS;
280 IFQ_SET_READY(&sc->sc_ifp->if_snd);
282 ether_ifattach(sc->sc_ifp, sc->sc_enaddr);
283 sc->sc_ifp->if_hwassist = 0;
287 mtx_destroy(&sc->sc_mtx);
293 glc_init_locked(struct glc_softc *sc)
296 struct glc_rxsoft *rxs;
297 struct glc_txsoft *txs;
299 mtx_assert(&sc->sc_mtx, MA_OWNED);
301 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
302 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0);
304 glc_set_multicast(sc);
306 for (i = 0; i < GLC_MAX_RX_PACKETS; i++) {
307 rxs = &sc->sc_rxsoft[i];
308 rxs->rxs_desc_slot = i;
310 if (rxs->rxs_mbuf == NULL) {
311 glc_add_rxbuf(sc, i);
313 if (rxs->rxs_mbuf == NULL) {
314 rxs->rxs_desc_slot = -1;
319 glc_add_rxbuf_dma(sc, i);
320 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
321 BUS_DMASYNC_PREREAD);
324 /* Clear TX dirty queue */
325 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
326 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
327 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap);
329 if (txs->txs_mbuf != NULL) {
330 m_freem(txs->txs_mbuf);
331 txs->txs_mbuf = NULL;
334 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
336 sc->first_used_txdma_slot = -1;
337 sc->bsy_txdma_slots = 0;
339 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev,
340 sc->sc_rxsoft[0].rxs_desc, 0);
342 device_printf(sc->sc_self,
343 "lv1_net_start_rx_dma error: %d\n", error);
345 sc->sc_ifp->if_drv_flags |= IFF_DRV_RUNNING;
346 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
347 sc->sc_ifpflags = sc->sc_ifp->if_flags;
349 sc->sc_wdog_timer = 0;
350 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc);
356 struct glc_softc *sc = xsc;
358 mtx_assert(&sc->sc_mtx, MA_OWNED);
360 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
361 lv1_net_stop_rx_dma(sc->sc_bus, sc->sc_dev, 0);
367 struct glc_softc *sc = xsc;
369 mtx_lock(&sc->sc_mtx);
371 mtx_unlock(&sc->sc_mtx);
377 struct glc_softc *sc = xsc;
379 mtx_assert(&sc->sc_mtx, MA_OWNED);
382 * XXX: Sometimes the RX queue gets stuck. Poke it periodically until
383 * we figure out why. This will fail harmlessly if the RX queue is
386 lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev,
387 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0);
389 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) {
390 callout_reset(&sc->sc_tick_ch, hz, glc_tick, sc);
395 device_printf(sc->sc_self, "device timeout\n");
401 glc_start_locked(struct ifnet *ifp)
403 struct glc_softc *sc = ifp->if_softc;
404 bus_addr_t first, pktdesc;
407 struct mbuf *mb_head;
409 mtx_assert(&sc->sc_mtx, MA_OWNED);
412 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
416 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
419 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
420 IFQ_DRV_DEQUEUE(&ifp->if_snd, mb_head);
425 /* Check if the ring buffer is full */
426 if (sc->bsy_txdma_slots > 125) {
427 /* Put the packet back and stop */
428 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
429 IFQ_DRV_PREPEND(&ifp->if_snd, mb_head);
433 BPF_MTAP(ifp, mb_head);
435 if (sc->sc_tx_vlan >= 0)
436 mb_head = ether_vlanencap(mb_head, sc->sc_tx_vlan);
438 if (glc_encap(sc, &mb_head, &pktdesc)) {
439 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
447 if (kickstart && first != 0) {
448 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev, first, 0);
450 device_printf(sc->sc_self,
451 "lv1_net_start_tx_dma error: %d\n", error);
452 sc->sc_wdog_timer = 5;
457 glc_start(struct ifnet *ifp)
459 struct glc_softc *sc = ifp->if_softc;
461 mtx_lock(&sc->sc_mtx);
462 glc_start_locked(ifp);
463 mtx_unlock(&sc->sc_mtx);
467 glc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
469 struct glc_softc *sc = ifp->if_softc;
470 struct ifreq *ifr = (struct ifreq *)data;
475 mtx_lock(&sc->sc_mtx);
476 if ((ifp->if_flags & IFF_UP) != 0) {
477 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
478 ((ifp->if_flags ^ sc->sc_ifpflags) &
479 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
480 glc_set_multicast(sc);
484 else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
486 sc->sc_ifpflags = ifp->if_flags;
487 mtx_unlock(&sc->sc_mtx);
491 mtx_lock(&sc->sc_mtx);
492 glc_set_multicast(sc);
493 mtx_unlock(&sc->sc_mtx);
497 err = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
500 err = ether_ioctl(ifp, cmd, data);
508 glc_add_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
510 struct glc_softc *sc = arg;
514 * Filter can only hold 32 addresses, so fall back to
515 * the IFF_ALLMULTI case if we have too many. +1 is for
522 memcpy(&((uint8_t *)(&addr))[2], LLADDR(sdl), ETHER_ADDR_LEN);
523 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, addr, 0);
529 glc_set_multicast(struct glc_softc *sc)
531 struct ifnet *ifp = sc->sc_ifp;
534 /* Clear multicast filter */
535 lv1_net_remove_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1);
538 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev,
541 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
542 lv1_net_add_multicast_address(sc->sc_bus, sc->sc_dev, 0, 1);
544 naddrs = if_foreach_llmaddr(ifp, glc_add_maddr, sc);
545 if (naddrs + 1 == 32)
546 lv1_net_add_multicast_address(sc->sc_bus,
552 glc_add_rxbuf(struct glc_softc *sc, int idx)
554 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx];
556 bus_dma_segment_t segs[1];
559 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
562 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
564 if (rxs->rxs_mbuf != NULL) {
565 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap,
566 BUS_DMASYNC_POSTREAD);
567 bus_dmamap_unload(sc->sc_rxdma_tag, rxs->rxs_dmamap);
570 error = bus_dmamap_load_mbuf_sg(sc->sc_rxdma_tag, rxs->rxs_dmamap, m,
571 segs, &nsegs, BUS_DMA_NOWAIT);
573 device_printf(sc->sc_self,
574 "cannot load RS DMA map %d, error = %d\n", idx, error);
578 /* If nsegs is wrong then the stack is corrupt. */
580 ("%s: too many DMA segments (%d)", __func__, nsegs));
582 rxs->segment = segs[0];
584 bus_dmamap_sync(sc->sc_rxdma_tag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
590 glc_add_rxbuf_dma(struct glc_softc *sc, int idx)
592 struct glc_rxsoft *rxs = &sc->sc_rxsoft[idx];
594 bzero(&sc->sc_rxdmadesc[idx], sizeof(sc->sc_rxdmadesc[idx]));
595 sc->sc_rxdmadesc[idx].paddr = rxs->segment.ds_addr;
596 sc->sc_rxdmadesc[idx].len = rxs->segment.ds_len;
597 sc->sc_rxdmadesc[idx].next = sc->sc_rxdmadesc_phys +
598 ((idx + 1) % GLC_MAX_RX_PACKETS)*sizeof(sc->sc_rxdmadesc[idx]);
599 sc->sc_rxdmadesc[idx].cmd_stat = GELIC_DESCR_OWNED;
601 rxs->rxs_desc_slot = idx;
602 rxs->rxs_desc = sc->sc_rxdmadesc_phys + idx*sizeof(struct glc_dmadesc);
608 glc_encap(struct glc_softc *sc, struct mbuf **m_head, bus_addr_t *pktdesc)
610 bus_dma_segment_t segs[16];
611 struct glc_txsoft *txs;
613 bus_addr_t firstslotphys;
614 int i, idx, nsegs, nsegs_max;
617 /* Max number of segments is the number of free DMA slots */
618 nsegs_max = 128 - sc->bsy_txdma_slots;
620 if (nsegs_max > 16 || sc->first_used_txdma_slot < 0)
623 /* Get a work queue entry. */
624 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
625 /* Ran out of descriptors. */
630 for (m = *m_head; m != NULL; m = m->m_next)
633 if (nsegs > nsegs_max) {
634 m = m_collapse(*m_head, M_NOWAIT, nsegs_max);
643 err = bus_dmamap_load_mbuf_sg(sc->sc_txdma_tag, txs->txs_dmamap,
644 *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
651 KASSERT(nsegs <= 128 - sc->bsy_txdma_slots,
652 ("GLC: Mapped too many (%d) DMA segments with %d available",
653 nsegs, 128 - sc->bsy_txdma_slots));
661 txs->txs_ndescs = nsegs;
662 txs->txs_firstdesc = sc->next_txdma_slot;
664 idx = txs->txs_firstdesc;
665 firstslotphys = sc->sc_txdmadesc_phys +
666 txs->txs_firstdesc*sizeof(struct glc_dmadesc);
668 for (i = 0; i < nsegs; i++) {
669 bzero(&sc->sc_txdmadesc[idx], sizeof(sc->sc_txdmadesc[idx]));
670 sc->sc_txdmadesc[idx].paddr = segs[i].ds_addr;
671 sc->sc_txdmadesc[idx].len = segs[i].ds_len;
672 sc->sc_txdmadesc[idx].next = sc->sc_txdmadesc_phys +
673 ((idx + 1) % GLC_MAX_TX_PACKETS)*sizeof(struct glc_dmadesc);
674 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_NOIPSEC;
677 txs->txs_lastdesc = idx;
678 sc->sc_txdmadesc[idx].next = 0;
679 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_LAST;
682 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
683 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_TCP;
684 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
685 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_CMDSTAT_CSUM_UDP;
686 sc->sc_txdmadesc[idx].cmd_stat |= GELIC_DESCR_OWNED;
688 idx = (idx + 1) % GLC_MAX_TX_PACKETS;
690 sc->next_txdma_slot = idx;
691 sc->bsy_txdma_slots += nsegs;
692 if (txs->txs_firstdesc != 0)
693 idx = txs->txs_firstdesc - 1;
695 idx = GLC_MAX_TX_PACKETS - 1;
697 if (sc->first_used_txdma_slot < 0)
698 sc->first_used_txdma_slot = txs->txs_firstdesc;
700 bus_dmamap_sync(sc->sc_txdma_tag, txs->txs_dmamap,
701 BUS_DMASYNC_PREWRITE);
702 sc->sc_txdmadesc[idx].next = firstslotphys;
704 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
705 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
706 txs->txs_mbuf = *m_head;
707 *pktdesc = firstslotphys;
713 glc_rxintr(struct glc_softc *sc)
715 int i, restart_rxdma, error;
717 struct ifnet *ifp = sc->sc_ifp;
719 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
720 BUS_DMASYNC_POSTREAD);
723 while ((sc->sc_rxdmadesc[sc->sc_next_rxdma_slot].cmd_stat &
724 GELIC_DESCR_OWNED) == 0) {
725 i = sc->sc_next_rxdma_slot;
726 sc->sc_next_rxdma_slot++;
727 if (sc->sc_next_rxdma_slot >= GLC_MAX_RX_PACKETS)
728 sc->sc_next_rxdma_slot = 0;
730 if (sc->sc_rxdmadesc[i].cmd_stat & GELIC_CMDSTAT_CHAIN_END)
733 if (sc->sc_rxdmadesc[i].rxerror & GELIC_RXERRORS) {
734 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
738 m = sc->sc_rxsoft[i].rxs_mbuf;
739 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_IPCSUM) {
740 m->m_pkthdr.csum_flags |=
741 CSUM_IP_CHECKED | CSUM_IP_VALID;
743 if (sc->sc_rxdmadesc[i].data_stat & GELIC_RX_TCPUDPCSUM) {
744 m->m_pkthdr.csum_flags |=
745 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
746 m->m_pkthdr.csum_data = 0xffff;
749 if (glc_add_rxbuf(sc, i)) {
750 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
754 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
755 m->m_pkthdr.rcvif = ifp;
756 m->m_len = sc->sc_rxdmadesc[i].valid_size;
757 m->m_pkthdr.len = m->m_len;
760 * Remove VLAN tag. Even on early firmwares that do not allow
761 * multiple VLANs, the VLAN tag is still in place here.
765 mtx_unlock(&sc->sc_mtx);
766 (*ifp->if_input)(ifp, m);
767 mtx_lock(&sc->sc_mtx);
770 glc_add_rxbuf_dma(sc, i);
773 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_rxdmadesc_map,
774 BUS_DMASYNC_PREWRITE);
777 error = lv1_net_start_rx_dma(sc->sc_bus, sc->sc_dev,
778 sc->sc_rxsoft[sc->sc_next_rxdma_slot].rxs_desc, 0);
780 device_printf(sc->sc_self,
781 "lv1_net_start_rx_dma error: %d\n", error);
786 glc_txintr(struct glc_softc *sc)
788 struct ifnet *ifp = sc->sc_ifp;
789 struct glc_txsoft *txs;
790 int progress = 0, kickstart = 0, error;
792 bus_dmamap_sync(sc->sc_dmadesc_tag, sc->sc_txdmadesc_map,
793 BUS_DMASYNC_POSTREAD);
795 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
796 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat
800 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
801 bus_dmamap_unload(sc->sc_txdma_tag, txs->txs_dmamap);
802 sc->bsy_txdma_slots -= txs->txs_ndescs;
804 if (txs->txs_mbuf != NULL) {
805 m_freem(txs->txs_mbuf);
806 txs->txs_mbuf = NULL;
809 if ((sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat & 0xf0000000)
811 lv1_net_stop_tx_dma(sc->sc_bus, sc->sc_dev, 0);
813 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
816 if (sc->sc_txdmadesc[txs->txs_lastdesc].cmd_stat &
817 GELIC_CMDSTAT_CHAIN_END)
820 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
821 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
826 sc->first_used_txdma_slot = txs->txs_firstdesc;
828 sc->first_used_txdma_slot = -1;
830 if (kickstart || txs != NULL) {
831 /* Speculatively (or necessarily) start the TX queue again */
832 error = lv1_net_start_tx_dma(sc->sc_bus, sc->sc_dev,
833 sc->sc_txdmadesc_phys +
834 ((txs == NULL) ? 0 : txs->txs_firstdesc)*
835 sizeof(struct glc_dmadesc), 0);
837 device_printf(sc->sc_self,
838 "lv1_net_start_tx_dma error: %d\n", error);
843 * We freed some descriptors, so reset IFF_DRV_OACTIVE
846 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
847 sc->sc_wdog_timer = STAILQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
849 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
850 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
851 glc_start_locked(ifp);
856 glc_intr_filter(void *xsc)
858 struct glc_softc *sc = xsc;
861 atomic_set_64(&sc->sc_interrupt_status, *sc->sc_hwirq_status);
862 return (FILTER_SCHEDULE_THREAD);
868 struct glc_softc *sc = xsc;
869 uint64_t status, linkstat, junk;
871 mtx_lock(&sc->sc_mtx);
873 status = atomic_readandclear_64(&sc->sc_interrupt_status);
876 mtx_unlock(&sc->sc_mtx);
880 if (status & (GELIC_INT_RXDONE | GELIC_INT_RXFRAME))
883 if (status & (GELIC_INT_TXDONE | GELIC_INT_TX_CHAIN_END))
886 if (status & GELIC_INT_PHY) {
887 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS,
888 GELIC_VLAN_TX_ETHERNET, 0, 0, &linkstat, &junk);
890 linkstat = (linkstat & GELIC_LINK_UP) ?
891 LINK_STATE_UP : LINK_STATE_DOWN;
892 if (linkstat != sc->sc_ifp->if_link_state)
893 if_link_state_change(sc->sc_ifp, linkstat);
896 mtx_unlock(&sc->sc_mtx);
900 glc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
902 struct glc_softc *sc = ifp->if_softc;
903 uint64_t status, junk;
905 ifmr->ifm_status = IFM_AVALID;
906 ifmr->ifm_active = IFM_ETHER;
908 lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_GET_LINK_STATUS,
909 GELIC_VLAN_TX_ETHERNET, 0, 0, &status, &junk);
911 if (status & GELIC_LINK_UP)
912 ifmr->ifm_status |= IFM_ACTIVE;
914 if (status & GELIC_SPEED_10)
915 ifmr->ifm_active |= IFM_10_T;
916 else if (status & GELIC_SPEED_100)
917 ifmr->ifm_active |= IFM_100_TX;
918 else if (status & GELIC_SPEED_1000)
919 ifmr->ifm_active |= IFM_1000_T;
921 if (status & GELIC_FULL_DUPLEX)
922 ifmr->ifm_active |= IFM_FDX;
924 ifmr->ifm_active |= IFM_HDX;
928 glc_media_change(struct ifnet *ifp)
930 struct glc_softc *sc = ifp->if_softc;
934 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
937 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)) {
939 mode = GELIC_AUTO_NEG;
942 mode = GELIC_SPEED_10;
945 mode = GELIC_SPEED_100;
948 mode = GELIC_SPEED_1000 | GELIC_FULL_DUPLEX;
954 if (IFM_OPTIONS(sc->sc_media.ifm_media) & IFM_FDX)
955 mode |= GELIC_FULL_DUPLEX;
957 result = lv1_net_control(sc->sc_bus, sc->sc_dev, GELIC_SET_LINK_MODE,
958 GELIC_VLAN_TX_ETHERNET, mode, 0, &junk, &junk);
960 return (result ? EIO : 0);