2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright 2011 Nathan Whitehorn
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include "opt_platform.h"
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/module.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
45 #include <machine/bus.h>
46 #include <machine/intr_machdep.h>
47 #include <machine/md_var.h>
48 #include <machine/rtas.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
54 #include <powerpc/powernv/opal.h>
57 #include "phyp-hvcall.h"
60 #define XICP_PRIORITY 5 /* Random non-zero number */
62 #define MAX_XICP_IRQS (1<<24) /* 24-bit XIRR field */
64 #define XIVE_XICS_MODE_EMU 0
65 #define XIVE_XICS_MODE_EXP 1
67 static int xicp_probe(device_t);
68 static int xicp_attach(device_t);
69 static int xics_probe(device_t);
70 static int xics_attach(device_t);
72 static void xicp_bind(device_t dev, u_int irq, cpuset_t cpumask);
73 static void xicp_dispatch(device_t, struct trapframe *);
74 static void xicp_enable(device_t, u_int, u_int);
75 static void xicp_eoi(device_t, u_int);
76 static void xicp_ipi(device_t, u_int);
77 static void xicp_mask(device_t, u_int);
78 static void xicp_unmask(device_t, u_int);
81 void xicp_smp_cpu_startup(void);
84 static device_method_t xicp_methods[] = {
85 /* Device interface */
86 DEVMETHOD(device_probe, xicp_probe),
87 DEVMETHOD(device_attach, xicp_attach),
90 DEVMETHOD(pic_bind, xicp_bind),
91 DEVMETHOD(pic_dispatch, xicp_dispatch),
92 DEVMETHOD(pic_enable, xicp_enable),
93 DEVMETHOD(pic_eoi, xicp_eoi),
94 DEVMETHOD(pic_ipi, xicp_ipi),
95 DEVMETHOD(pic_mask, xicp_mask),
96 DEVMETHOD(pic_unmask, xicp_unmask),
101 static device_method_t xics_methods[] = {
102 /* Device interface */
103 DEVMETHOD(device_probe, xics_probe),
104 DEVMETHOD(device_attach, xics_attach),
111 struct resource *mem[MAXCPU];
120 /* XXX: inefficient -- hash table? tree? */
130 static driver_t xicp_driver = {
133 sizeof(struct xicp_softc)
136 static driver_t xics_driver = {
143 /* We can only pass physical addresses into OPAL. Kernel stacks are in the KVA,
144 * not in the direct map, so we need to somehow extract the physical address.
145 * However, pmap_kextract() takes locks, which is forbidden in a critical region
146 * (which PIC_DISPATCH() operates in). The kernel is mapped into the Direct
147 * Map (0xc000....), and the CPU implicitly drops the top two bits when doing
148 * real address by nature that the bus width is smaller than 64-bits. Placing
149 * cpu_xirr into the DMAP lets us take advantage of this and avoids the
150 * pmap_kextract() that would otherwise be needed if using the stack variable.
152 static uint32_t cpu_xirr[MAXCPU];
155 static devclass_t xicp_devclass;
156 static devclass_t xics_devclass;
158 EARLY_DRIVER_MODULE(xicp, ofwbus, xicp_driver, xicp_devclass, 0, 0,
159 BUS_PASS_INTERRUPT-1);
160 EARLY_DRIVER_MODULE(xics, ofwbus, xics_driver, xics_devclass, 0, 0,
164 static struct resource *
165 xicp_mem_for_cpu(int cpu)
168 struct xicp_softc *sc;
171 for (i = 0; (dev = devclass_get_device(xicp_devclass, i)) != NULL; i++){
172 sc = device_get_softc(dev);
173 if (cpu >= sc->cpu_range[0] && cpu < sc->cpu_range[1])
174 return (sc->mem[cpu - sc->cpu_range[0]]);
182 xicp_probe(device_t dev)
185 if (!ofw_bus_is_compatible(dev, "ibm,ppc-xicp") &&
186 !ofw_bus_is_compatible(dev, "ibm,opal-intc"))
189 device_set_desc(dev, "External Interrupt Presentation Controller");
190 return (BUS_PROBE_GENERIC);
194 xics_probe(device_t dev)
197 if (!ofw_bus_is_compatible(dev, "ibm,ppc-xics") &&
198 !ofw_bus_is_compatible(dev, "IBM,opal-xics"))
201 device_set_desc(dev, "External Interrupt Source Controller");
202 return (BUS_PROBE_GENERIC);
206 xicp_attach(device_t dev)
208 struct xicp_softc *sc = device_get_softc(dev);
209 phandle_t phandle = ofw_bus_get_node(dev);
212 sc->ibm_int_on = rtas_token_lookup("ibm,int-on");
213 sc->ibm_int_off = rtas_token_lookup("ibm,int-off");
214 sc->ibm_set_xive = rtas_token_lookup("ibm,set-xive");
215 sc->ibm_get_xive = rtas_token_lookup("ibm,get-xive");
217 } else if (opal_check() == 0) {
221 device_printf(dev, "Cannot attach without RTAS or OPAL\n");
225 if (OF_hasprop(phandle, "ibm,interrupt-server-ranges")) {
226 OF_getencprop(phandle, "ibm,interrupt-server-ranges",
227 sc->cpu_range, sizeof(sc->cpu_range));
228 sc->cpu_range[1] += sc->cpu_range[0];
229 device_printf(dev, "Handling CPUs %d-%d\n", sc->cpu_range[0],
232 } else if (ofw_bus_is_compatible(dev, "ibm,opal-intc")) {
234 * For now run POWER9 XIVE interrupt controller in XICS
235 * compatibility mode.
238 opal_call(OPAL_XIVE_RESET, XIVE_XICS_MODE_EMU);
241 sc->cpu_range[0] = 0;
242 sc->cpu_range[1] = mp_ncpus;
246 if (mfmsr() & PSL_HV) {
250 opal_call(OPAL_INT_SET_CPPR, 0xff);
251 for (i = 0; i < mp_ncpus; i++) {
252 opal_call(OPAL_INT_SET_MFRR,
253 pcpu_find(i)->pc_hwref, 0xff);
256 for (i = 0; i < sc->cpu_range[1] - sc->cpu_range[0]; i++) {
257 sc->mem[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
259 if (sc->mem[i] == NULL) {
260 device_printf(dev, "Could not alloc mem "
265 /* Unmask interrupts on all cores */
266 bus_write_1(sc->mem[i], 4, 0xff);
267 bus_write_1(sc->mem[i], 12, 0xff);
273 mtx_init(&sc->sc_mtx, "XICP", NULL, MTX_DEF);
276 powerpc_register_pic(dev, OF_xref_from_node(phandle), MAX_XICP_IRQS,
277 1 /* Number of IPIs */, FALSE);
284 xics_attach(device_t dev)
286 phandle_t phandle = ofw_bus_get_node(dev);
288 /* The XICP (root PIC) will handle all our interrupts */
289 powerpc_register_pic(root_pic, OF_xref_from_node(phandle),
290 MAX_XICP_IRQS, 1 /* Number of IPIs */, FALSE);
300 xicp_bind(device_t dev, u_int irq, cpuset_t cpumask)
302 struct xicp_softc *sc = device_get_softc(dev);
307 if (irq == MAX_XICP_IRQS)
311 * This doesn't appear to actually support affinity groups, so pick a
316 if (CPU_ISSET(cpu, &cpumask)) ncpus++;
321 if (!CPU_ISSET(cpu, &cpumask))
328 cpu = pcpu_find(cpu)->pc_hwref;
330 /* XXX: super inefficient */
331 for (i = 0; i < sc->nintvecs; i++) {
332 if (sc->intvecs[i].irq == irq) {
333 sc->intvecs[i].cpu = cpu;
337 KASSERT(i < sc->nintvecs, ("Binding non-configured interrupt"));
340 error = rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
341 XICP_PRIORITY, &status);
344 error = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
348 panic("Cannot bind interrupt %d to CPU %d", irq, cpu);
352 xicp_dispatch(device_t dev, struct trapframe *tf)
354 struct xicp_softc *sc;
355 struct resource *regs = NULL;
359 sc = device_get_softc(dev);
361 if ((mfmsr() & PSL_HV) && !sc->xics_emu) {
362 regs = xicp_mem_for_cpu(PCPU_GET(hwref));
363 KASSERT(regs != NULL,
364 ("Can't find regs for CPU %ld", (uintptr_t)PCPU_GET(hwref)));
369 /* Return value in R4, use the PFT call */
371 xirr = bus_read_4(regs, 4);
373 } else if (sc->xics_emu) {
374 opal_call(OPAL_INT_GET_XIRR, &cpu_xirr[PCPU_GET(cpuid)],
376 xirr = cpu_xirr[PCPU_GET(cpuid)];
379 /* Return value in R4, use the PFT call */
380 phyp_pft_hcall(H_XIRR, 0, 0, 0, 0, &xirr, &junk, &junk);
384 if (xirr == 0) /* No more pending interrupts? */
387 if (xirr == XICP_IPI) { /* Magic number for IPIs */
388 xirr = MAX_XICP_IRQS; /* Map to FreeBSD magic */
392 bus_write_1(regs, 12, 0xff);
394 else if (sc->xics_emu)
395 opal_call(OPAL_INT_SET_MFRR,
396 PCPU_GET(hwref), 0xff);
399 phyp_hcall(H_IPI, (uint64_t)(PCPU_GET(hwref)),
403 /* XXX: super inefficient */
404 for (i = 0; i < sc->nintvecs; i++) {
405 if (sc->intvecs[i].irq == xirr)
409 KASSERT(i < sc->nintvecs, ("Unmapped XIRR"));
410 powerpc_dispatch_intr(sc->intvecs[i].vector, tf);
415 xicp_enable(device_t dev, u_int irq, u_int vector)
417 struct xicp_softc *sc;
420 sc = device_get_softc(dev);
422 KASSERT(sc->nintvecs + 1 < nitems(sc->intvecs),
423 ("Too many XICP interrupts"));
425 /* Bind to this CPU to start: distrib. ID is last entry in gserver# */
426 cpu = PCPU_GET(hwref);
428 mtx_lock(&sc->sc_mtx);
429 sc->intvecs[sc->nintvecs].irq = irq;
430 sc->intvecs[sc->nintvecs].vector = vector;
431 sc->intvecs[sc->nintvecs].cpu = cpu;
434 mtx_unlock(&sc->sc_mtx);
436 /* IPIs are also enabled */
437 if (irq == MAX_XICP_IRQS)
441 rtas_call_method(sc->ibm_set_xive, 3, 1, irq, cpu,
442 XICP_PRIORITY, &status);
443 xicp_unmask(dev, irq);
446 status = opal_call(OPAL_SET_XIVE, irq, cpu << 2, XICP_PRIORITY);
447 /* Unmask implicit for OPAL */
450 panic("OPAL_SET_XIVE IRQ %d -> cpu %d failed: %d", irq,
457 xicp_eoi(device_t dev, u_int irq)
460 struct xicp_softc *sc;
464 if (irq == MAX_XICP_IRQS) /* Remap IPI interrupt to internal value */
466 xirr = irq | (0xff << 24);
469 if (mfmsr() & PSL_HV) {
470 sc = device_get_softc(dev);
472 opal_call(OPAL_INT_EOI, xirr);
474 bus_write_4(xicp_mem_for_cpu(PCPU_GET(hwref)), 4, xirr);
477 phyp_hcall(H_EOI, xirr);
481 xicp_ipi(device_t dev, u_int cpu)
485 struct xicp_softc *sc;
486 cpu = pcpu_find(cpu)->pc_hwref;
488 if (mfmsr() & PSL_HV) {
489 sc = device_get_softc(dev);
492 rv = opal_call(OPAL_INT_SET_MFRR, cpu, XICP_PRIORITY);
494 device_printf(dev, "IPI SET_MFRR result: %ld\n", rv);
496 bus_write_1(xicp_mem_for_cpu(cpu), 12, XICP_PRIORITY);
499 phyp_hcall(H_IPI, (uint64_t)cpu, XICP_PRIORITY);
503 xicp_mask(device_t dev, u_int irq)
505 struct xicp_softc *sc = device_get_softc(dev);
508 if (irq == MAX_XICP_IRQS)
512 rtas_call_method(sc->ibm_int_off, 1, 1, irq, &status);
517 for (i = 0; i < sc->nintvecs; i++) {
518 if (sc->intvecs[i].irq == irq) {
522 KASSERT(i < sc->nintvecs, ("Masking unconfigured interrupt"));
523 opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2, 0xff);
529 xicp_unmask(device_t dev, u_int irq)
531 struct xicp_softc *sc = device_get_softc(dev);
534 if (irq == MAX_XICP_IRQS)
538 rtas_call_method(sc->ibm_int_on, 1, 1, irq, &status);
543 for (i = 0; i < sc->nintvecs; i++) {
544 if (sc->intvecs[i].irq == irq) {
548 KASSERT(i < sc->nintvecs, ("Unmasking unconfigured interrupt"));
549 opal_call(OPAL_SET_XIVE, irq, sc->intvecs[i].cpu << 2,
556 /* This is only used on POWER9 systems with the XIVE's XICS emulation. */
558 xicp_smp_cpu_startup(void)
560 struct xicp_softc *sc;
562 if (mfmsr() & PSL_HV) {
563 sc = device_get_softc(root_pic);
566 opal_call(OPAL_INT_SET_CPPR, 0xff);