2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #ifndef _MACHINE_CPUFUNC_H_
38 #define _MACHINE_CPUFUNC_H_
49 #include <machine/riscvreg.h>
51 static __inline register_t
57 "csrrci %0, sstatus, %1"
58 : "=&r" (ret) : "i" (SSTATUS_SIE)
61 return (ret & (SSTATUS_SIE));
65 intr_restore(register_t s)
84 /* NB: fence() is defined as a macro in <machine/atomic.h>. */
90 __asm __volatile("fence.i" ::: "memory");
97 __asm __volatile("sfence.vma" ::: "memory");
101 sfence_vma_page(uintptr_t addr)
104 __asm __volatile("sfence.vma %0" :: "r" (addr) : "memory");
107 #define rdcycle() csr_read64(cycle)
108 #define rdtime() csr_read64(time)
109 #define rdinstret() csr_read64(instret)
110 #define rdhpmcounter(n) csr_read64(hpmcounter##n)
112 extern int64_t dcache_line_size;
113 extern int64_t icache_line_size;
115 #define cpu_dcache_wbinv_range(a, s)
116 #define cpu_dcache_inv_range(a, s)
117 #define cpu_dcache_wb_range(a, s)
119 #define cpu_idcache_wbinv_range(a, s)
120 #define cpu_icache_sync_range(a, s)
121 #define cpu_icache_sync_range_checked(a, s)
123 #define cpufunc_nullop() riscv_nullop()
125 void riscv_nullop(void);
128 #endif /* _MACHINE_CPUFUNC_H_ */