2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
6 * Portions of this software were developed by SRI International and the
7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
10 * Portions of this software were developed by the University of Cambridge
11 * Computer Laboratory as part of the CTSRD Project, with support from the
12 * UK Higher Education Innovation Fund (HEIF).
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #ifndef _MACHINE_PTE_H_
37 #define _MACHINE_PTE_H_
40 typedef uint64_t pd_entry_t; /* page directory entry */
41 typedef uint64_t pt_entry_t; /* page table entry */
42 typedef uint64_t pn_t; /* page number */
45 /* Level 0 table, 512GiB per entry, SV48 only */
47 #define L0_SIZE (1UL << L0_SHIFT)
48 #define L0_OFFSET (L0_SIZE - 1)
50 /* Level 1 table, 1GiB per entry */
52 #define L1_SIZE (1UL << L1_SHIFT)
53 #define L1_OFFSET (L1_SIZE - 1)
55 /* Level 2 table, 2MiB per entry */
57 #define L2_SIZE (1UL << L2_SHIFT)
58 #define L2_OFFSET (L2_SIZE - 1)
60 /* Level 3 table, 4KiB per entry */
62 #define L3_SIZE (1UL << L3_SHIFT)
63 #define L3_OFFSET (L3_SIZE - 1)
65 #define Ln_ENTRIES_SHIFT 9
66 #define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
67 #define Ln_ADDR_MASK (Ln_ENTRIES - 1)
69 /* Bits 9:8 are reserved for software */
70 #define PTE_SW_MANAGED (1 << 9)
71 #define PTE_SW_WIRED (1 << 8)
72 #define PTE_D (1 << 7) /* Dirty */
73 #define PTE_A (1 << 6) /* Accessed */
74 #define PTE_G (1 << 5) /* Global */
75 #define PTE_U (1 << 4) /* User */
76 #define PTE_X (1 << 3) /* Execute */
77 #define PTE_W (1 << 2) /* Write */
78 #define PTE_R (1 << 1) /* Read */
79 #define PTE_V (1 << 0) /* Valid */
80 #define PTE_RWX (PTE_R | PTE_W | PTE_X)
81 #define PTE_RX (PTE_R | PTE_X)
82 #define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D)
83 #define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_G | PTE_U | \
84 PTE_SW_MANAGED | PTE_SW_WIRED)
86 /* Bits 63 - 54 are reserved for future use. */
87 #define PTE_HI_MASK 0xFFC0000000000000ULL
95 #endif /* !_MACHINE_PTE_H_ */