2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #ifndef _MACHINE_RISCVREG_H_
38 #define _MACHINE_RISCVREG_H_
41 #define EXCP_MASK (0xf << EXCP_SHIFT)
42 #define EXCP_MISALIGNED_FETCH 0
43 #define EXCP_FAULT_FETCH 1
44 #define EXCP_ILLEGAL_INSTRUCTION 2
45 #define EXCP_BREAKPOINT 3
46 #define EXCP_MISALIGNED_LOAD 4
47 #define EXCP_FAULT_LOAD 5
48 #define EXCP_MISALIGNED_STORE 6
49 #define EXCP_FAULT_STORE 7
50 #define EXCP_USER_ECALL 8
51 #define EXCP_SUPERVISOR_ECALL 9
52 #define EXCP_HYPERVISOR_ECALL 10
53 #define EXCP_MACHINE_ECALL 11
54 #define EXCP_INTR (1ul << 63)
56 #define SSTATUS_UIE (1 << 0)
57 #define SSTATUS_SIE (1 << 1)
58 #define SSTATUS_UPIE (1 << 4)
59 #define SSTATUS_SPIE (1 << 5)
60 #define SSTATUS_SPIE_SHIFT 5
61 #define SSTATUS_SPP (1 << 8)
62 #define SSTATUS_SPP_SHIFT 8
63 #define SSTATUS_FS_SHIFT 13
64 #define SSTATUS_FS_OFF (0x0 << SSTATUS_FS_SHIFT)
65 #define SSTATUS_FS_INITIAL (0x1 << SSTATUS_FS_SHIFT)
66 #define SSTATUS_FS_CLEAN (0x2 << SSTATUS_FS_SHIFT)
67 #define SSTATUS_FS_DIRTY (0x3 << SSTATUS_FS_SHIFT)
68 #define SSTATUS_FS_MASK (0x3 << SSTATUS_FS_SHIFT)
69 #define SSTATUS_XS_SHIFT 15
70 #define SSTATUS_XS_MASK (0x3 << SSTATUS_XS_SHIFT)
71 #define SSTATUS_PUM (1 << 18)
72 #define SSTATUS32_SD (1 << 63)
73 #define SSTATUS64_SD (1 << 31)
75 #define MSTATUS_UIE (1 << 0)
76 #define MSTATUS_SIE (1 << 1)
77 #define MSTATUS_HIE (1 << 2)
78 #define MSTATUS_MIE (1 << 3)
79 #define MSTATUS_UPIE (1 << 4)
80 #define MSTATUS_SPIE (1 << 5)
81 #define MSTATUS_SPIE_SHIFT 5
82 #define MSTATUS_HPIE (1 << 6)
83 #define MSTATUS_MPIE (1 << 7)
84 #define MSTATUS_MPIE_SHIFT 7
85 #define MSTATUS_SPP (1 << 8)
86 #define MSTATUS_SPP_SHIFT 8
87 #define MSTATUS_HPP_MASK 0x3
88 #define MSTATUS_HPP_SHIFT 9
89 #define MSTATUS_MPP_MASK 0x3
90 #define MSTATUS_MPP_SHIFT 11
91 #define MSTATUS_FS_MASK 0x3
92 #define MSTATUS_FS_SHIFT 13
93 #define MSTATUS_XS_MASK 0x3
94 #define MSTATUS_XS_SHIFT 15
95 #define MSTATUS_MPRV (1 << 17)
96 #define MSTATUS_PUM (1 << 18)
97 #define MSTATUS_VM_MASK 0x1f
98 #define MSTATUS_VM_SHIFT 24
99 #define MSTATUS_VM_MBARE 0
100 #define MSTATUS_VM_MBB 1
101 #define MSTATUS_VM_MBBID 2
102 #define MSTATUS_VM_SV32 8
103 #define MSTATUS_VM_SV39 9
104 #define MSTATUS_VM_SV48 10
105 #define MSTATUS_VM_SV57 11
106 #define MSTATUS_VM_SV64 12
107 #define MSTATUS32_SD (1 << 63)
108 #define MSTATUS64_SD (1 << 31)
110 #define MSTATUS_PRV_U 0 /* user */
111 #define MSTATUS_PRV_S 1 /* supervisor */
112 #define MSTATUS_PRV_H 2 /* hypervisor */
113 #define MSTATUS_PRV_M 3 /* machine */
115 #define MIE_USIE (1 << 0)
116 #define MIE_SSIE (1 << 1)
117 #define MIE_HSIE (1 << 2)
118 #define MIE_MSIE (1 << 3)
119 #define MIE_UTIE (1 << 4)
120 #define MIE_STIE (1 << 5)
121 #define MIE_HTIE (1 << 6)
122 #define MIE_MTIE (1 << 7)
124 #define MIP_USIP (1 << 0)
125 #define MIP_SSIP (1 << 1)
126 #define MIP_HSIP (1 << 2)
127 #define MIP_MSIP (1 << 3)
128 #define MIP_UTIP (1 << 4)
129 #define MIP_STIP (1 << 5)
130 #define MIP_HTIP (1 << 6)
131 #define MIP_MTIP (1 << 7)
133 #define SIE_USIE (1 << 0)
134 #define SIE_SSIE (1 << 1)
135 #define SIE_UTIE (1 << 4)
136 #define SIE_STIE (1 << 5)
138 #define MIP_SEIP (1 << 9)
140 /* Note: sip register has no SIP_STIP bit in Spike simulator */
141 #define SIP_SSIP (1 << 1)
142 #define SIP_STIP (1 << 5)
147 #define CSR_IPI 0x783
148 #define CSR_IO_IRQ 0x7c0 /* lowRISC only? */
154 #define RISCV_INSN_NOP 0x00000013
155 #define RISCV_INSN_BREAK 0x00100073
156 #define RISCV_INSN_RET 0x00008067
158 #define CSR_ZIMM(val) \
159 (__builtin_constant_p(val) && ((u_long)(val) < 32))
161 #define csr_swap(csr, val) \
162 ({ if (CSR_ZIMM(val)) \
163 __asm __volatile("csrrwi %0, " #csr ", %1" \
164 : "=r" (val) : "i" (val)); \
166 __asm __volatile("csrrw %0, " #csr ", %1" \
167 : "=r" (val) : "r" (val)); \
171 #define csr_write(csr, val) \
172 ({ if (CSR_ZIMM(val)) \
173 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
175 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
178 #define csr_set(csr, val) \
179 ({ if (CSR_ZIMM(val)) \
180 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
182 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
185 #define csr_clear(csr, val) \
186 ({ if (CSR_ZIMM(val)) \
187 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \
189 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \
192 #define csr_read(csr) \
194 __asm __volatile("csrr %0, " #csr : "=r" (val)); \
198 #endif /* !_MACHINE_RISCVREG_H_ */