2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #ifndef _MACHINE_RISCVREG_H_
38 #define _MACHINE_RISCVREG_H_
40 #define SCAUSE_INTR (1ul << 63)
41 #define SCAUSE_CODE (~SCAUSE_INTR)
42 #define SCAUSE_INST_MISALIGNED 0
43 #define SCAUSE_INST_ACCESS_FAULT 1
44 #define SCAUSE_ILLEGAL_INSTRUCTION 2
45 #define SCAUSE_BREAKPOINT 3
46 #define SCAUSE_LOAD_MISALIGNED 4
47 #define SCAUSE_LOAD_ACCESS_FAULT 5
48 #define SCAUSE_STORE_MISALIGNED 6
49 #define SCAUSE_STORE_ACCESS_FAULT 7
50 #define SCAUSE_ECALL_USER 8
51 #define SCAUSE_ECALL_SUPERVISOR 9
52 #define SCAUSE_INST_PAGE_FAULT 12
53 #define SCAUSE_LOAD_PAGE_FAULT 13
54 #define SCAUSE_STORE_PAGE_FAULT 15
56 #define SSTATUS_UIE (1 << 0)
57 #define SSTATUS_SIE (1 << 1)
58 #define SSTATUS_UPIE (1 << 4)
59 #define SSTATUS_SPIE (1 << 5)
60 #define SSTATUS_SPIE_SHIFT 5
61 #define SSTATUS_SPP (1 << 8)
62 #define SSTATUS_SPP_SHIFT 8
63 #define SSTATUS_FS_SHIFT 13
64 #define SSTATUS_FS_OFF (0x0 << SSTATUS_FS_SHIFT)
65 #define SSTATUS_FS_INITIAL (0x1 << SSTATUS_FS_SHIFT)
66 #define SSTATUS_FS_CLEAN (0x2 << SSTATUS_FS_SHIFT)
67 #define SSTATUS_FS_DIRTY (0x3 << SSTATUS_FS_SHIFT)
68 #define SSTATUS_FS_MASK (0x3 << SSTATUS_FS_SHIFT)
69 #define SSTATUS_XS_SHIFT 15
70 #define SSTATUS_XS_MASK (0x3 << SSTATUS_XS_SHIFT)
71 #define SSTATUS_SUM (1 << 18)
72 #if __riscv_xlen == 64
73 #define SSTATUS_SD (1ul << 63)
75 #define SSTATUS_SD (1 << 31)
78 #define MSTATUS_UIE (1 << 0)
79 #define MSTATUS_SIE (1 << 1)
80 #define MSTATUS_HIE (1 << 2)
81 #define MSTATUS_MIE (1 << 3)
82 #define MSTATUS_UPIE (1 << 4)
83 #define MSTATUS_SPIE (1 << 5)
84 #define MSTATUS_SPIE_SHIFT 5
85 #define MSTATUS_HPIE (1 << 6)
86 #define MSTATUS_MPIE (1 << 7)
87 #define MSTATUS_MPIE_SHIFT 7
88 #define MSTATUS_SPP (1 << 8)
89 #define MSTATUS_SPP_SHIFT 8
90 #define MSTATUS_HPP_MASK 0x3
91 #define MSTATUS_HPP_SHIFT 9
92 #define MSTATUS_MPP_MASK 0x3
93 #define MSTATUS_MPP_SHIFT 11
94 #define MSTATUS_FS_MASK 0x3
95 #define MSTATUS_FS_SHIFT 13
96 #define MSTATUS_XS_MASK 0x3
97 #define MSTATUS_XS_SHIFT 15
98 #define MSTATUS_MPRV (1 << 17)
99 #define MSTATUS_PUM (1 << 18)
100 #define MSTATUS_VM_MASK 0x1f
101 #define MSTATUS_VM_SHIFT 24
102 #define MSTATUS_VM_MBARE 0
103 #define MSTATUS_VM_MBB 1
104 #define MSTATUS_VM_MBBID 2
105 #define MSTATUS_VM_SV32 8
106 #define MSTATUS_VM_SV39 9
107 #define MSTATUS_VM_SV48 10
108 #define MSTATUS_VM_SV57 11
109 #define MSTATUS_VM_SV64 12
110 #if __riscv_xlen == 64
111 #define MSTATUS_SD (1ul << 63)
113 #define MSTATUS_SD (1 << 31)
116 #define MSTATUS_PRV_U 0 /* user */
117 #define MSTATUS_PRV_S 1 /* supervisor */
118 #define MSTATUS_PRV_H 2 /* hypervisor */
119 #define MSTATUS_PRV_M 3 /* machine */
121 #define MIE_USIE (1 << 0)
122 #define MIE_SSIE (1 << 1)
123 #define MIE_HSIE (1 << 2)
124 #define MIE_MSIE (1 << 3)
125 #define MIE_UTIE (1 << 4)
126 #define MIE_STIE (1 << 5)
127 #define MIE_HTIE (1 << 6)
128 #define MIE_MTIE (1 << 7)
130 #define MIP_USIP (1 << 0)
131 #define MIP_SSIP (1 << 1)
132 #define MIP_HSIP (1 << 2)
133 #define MIP_MSIP (1 << 3)
134 #define MIP_UTIP (1 << 4)
135 #define MIP_STIP (1 << 5)
136 #define MIP_HTIP (1 << 6)
137 #define MIP_MTIP (1 << 7)
139 #define SIE_USIE (1 << 0)
140 #define SIE_SSIE (1 << 1)
141 #define SIE_UTIE (1 << 4)
142 #define SIE_STIE (1 << 5)
143 #define SIE_UEIE (1 << 8)
144 #define SIE_SEIE (1 << 9)
146 #define MIP_SEIP (1 << 9)
148 /* Note: sip register has no SIP_STIP bit in Spike simulator */
149 #define SIP_SSIP (1 << 1)
150 #define SIP_STIP (1 << 5)
153 #define SATP_PPN_M (0xfffffffffff << SATP_PPN_S)
154 #define SATP_ASID_S 44
155 #define SATP_ASID_M (0xffff << SATP_ASID_S)
156 #define SATP_MODE_S 60
157 #define SATP_MODE_M (0xf << SATP_MODE_S)
158 #define SATP_MODE_SV39 (8ULL << SATP_MODE_S)
159 #define SATP_MODE_SV48 (9ULL << SATP_MODE_S)
161 #define XLEN __riscv_xlen
162 #define XLEN_BYTES (XLEN / 8)
164 #define INSN_C_SIZE 2
176 #define RD_MASK (0x1f << RD_SHIFT)
178 #define RS1_MASK (0x1f << RS1_SHIFT)
179 #define RS1_SP (X_SP << RS1_SHIFT)
181 #define RS2_MASK (0x1f << RS2_SHIFT)
182 #define RS2_RA (X_RA << RS2_SHIFT)
184 #define IMM_MASK (0xfff << IMM_SHIFT)
186 #define RS2_C_SHIFT 2
187 #define RS2_C_MASK (0x1f << RS2_C_SHIFT)
188 #define RS2_C_RA (X_RA << RS2_C_SHIFT)
190 #define CSR_ZIMM(val) \
191 (__builtin_constant_p(val) && ((u_long)(val) < 32))
193 #define csr_swap(csr, val) \
194 ({ if (CSR_ZIMM(val)) \
195 __asm __volatile("csrrwi %0, " #csr ", %1" \
196 : "=r" (val) : "i" (val)); \
198 __asm __volatile("csrrw %0, " #csr ", %1" \
199 : "=r" (val) : "r" (val)); \
203 #define csr_write(csr, val) \
204 ({ if (CSR_ZIMM(val)) \
205 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \
207 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \
210 #define csr_set(csr, val) \
211 ({ if (CSR_ZIMM(val)) \
212 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \
214 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \
217 #define csr_clear(csr, val) \
218 ({ if (CSR_ZIMM(val)) \
219 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \
221 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \
224 #define csr_read(csr) \
226 __asm __volatile("csrr %0, " #csr : "=r" (val)); \
230 #if __riscv_xlen == 32
231 #define csr_read64(csr) \
233 uint32_t high, low; \
234 __asm __volatile("1: " \
235 "csrr t0, " #csr "h\n" \
236 "csrr %0, " #csr "\n" \
237 "csrr %1, " #csr "h\n" \
239 : "=r" (low), "=r" (high) \
242 val = (low | ((uint64_t)high << 32)); \
246 #define csr_read64(csr) ((uint64_t)csr_read(csr))
249 #endif /* !_MACHINE_RISCVREG_H_ */