2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
6 * Copyright (c) 2022 Mitchell Horne <mhorne@FreeBSD.org>
7 * Copyright (c) 2023 The FreeBSD Foundation
9 * Portions of this software were developed by SRI International and the
10 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
13 * Portions of this software were developed by the University of Cambridge
14 * Computer Laboratory as part of the CTSRD Project, with support from the
15 * UK Higher Education Innovation Fund (HEIF).
17 * Portions of this software were developed by Mitchell Horne
18 * <mhorne@FreeBSD.org> under sponsorship from the FreeBSD Foundation.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
23 * 1. Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * 2. Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
30 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
32 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
38 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
42 #include "opt_platform.h"
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/ctype.h>
47 #include <sys/kernel.h>
49 #include <sys/sysctl.h>
51 #include <machine/cpu.h>
52 #include <machine/cpufunc.h>
53 #include <machine/elf.h>
54 #include <machine/md_var.h>
57 #include <dev/fdt/fdt_common.h>
58 #include <dev/ofw/openfirm.h>
59 #include <dev/ofw/ofw_bus_subr.h>
62 char machine[] = "riscv";
64 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD | CTLFLAG_CAPRD, machine, 0,
67 /* Hardware implementation info. These values may be empty. */
68 register_t mvendorid; /* The CPU's JEDEC vendor ID */
69 register_t marchid; /* The architecture ID */
70 register_t mimpid; /* The implementation ID */
74 /* Supervisor-mode extension support. */
75 bool __read_frequently has_sstc;
76 bool __read_frequently has_sscofpmf;
79 const char *cpu_mvendor_name;
80 const char *cpu_march_name;
81 u_int isa_extensions; /* Single-letter extensions. */
83 u_int smode_extensions;
84 #define SV_SSTC (1 << 0)
85 #define SV_SVNAPOT (1 << 1)
86 #define SV_SVPBMT (1 << 2)
87 #define SV_SVINVAL (1 << 3)
88 #define SV_SSCOFPMF (1 << 4)
91 struct cpu_desc cpu_desc[MAXCPU];
94 * Micro-architecture tables.
96 struct marchid_entry {
98 const char *march_name;
101 #define MARCHID_END { -1ul, NULL }
103 /* Open-source RISC-V architecture IDs; globally allocated. */
104 static const struct marchid_entry global_marchids[] = {
105 { MARCHID_UCB_ROCKET, "UC Berkeley Rocket" },
106 { MARCHID_UCB_BOOM, "UC Berkeley Boom" },
107 { MARCHID_UCB_SPIKE, "UC Berkeley Spike" },
108 { MARCHID_UCAM_RVBS, "University of Cambridge RVBS" },
112 static const struct marchid_entry sifive_marchids[] = {
113 { MARCHID_SIFIVE_U7, "6/7/P200/X200-Series Processor" },
118 * Known CPU vendor/manufacturer table.
120 static const struct {
121 register_t mvendor_id;
122 const char *mvendor_name;
123 const struct marchid_entry *marchid_table;
125 { MVENDORID_UNIMPL, "Unspecified", NULL },
126 { MVENDORID_SIFIVE, "SiFive", sifive_marchids },
127 { MVENDORID_THEAD, "T-Head", NULL },
131 * The ISA string describes the complete set of instructions supported by a
132 * RISC-V CPU. The string begins with a small prefix (e.g. rv64) indicating the
133 * base ISA. It is followed first by single-letter ISA extensions, and then
134 * multi-letter ISA extensions.
136 * Underscores are used mainly to separate consecutive multi-letter extensions,
137 * but may optionally appear between any two extensions. An extension may be
138 * followed by a version number, in the form of 'Mpm', where M is the
139 * extension's major version number, and 'm' is the minor version number.
141 * The format is described in detail by the "ISA Extension Naming Conventions"
142 * chapter of the unprivileged spec.
144 #define ISA_PREFIX ("rv" __XSTRING(__riscv_xlen))
145 #define ISA_PREFIX_LEN (sizeof(ISA_PREFIX) - 1)
148 parse_ext_s(struct cpu_desc *desc, char *isa, int idx, int len)
150 #define CHECK_S_EXT(str, flag) \
152 if (strncmp(&isa[idx], (str), \
153 MIN(strlen(str), len - idx)) == 0) { \
154 desc->smode_extensions |= flag; \
155 return (idx + strlen(str)); \
159 /* Check for known/supported extensions. */
160 CHECK_S_EXT("sstc", SV_SSTC);
161 CHECK_S_EXT("svnapot", SV_SVNAPOT);
162 CHECK_S_EXT("svpbmt", SV_SVPBMT);
163 CHECK_S_EXT("svinval", SV_SVINVAL);
164 CHECK_S_EXT("sscofpmf", SV_SSCOFPMF);
169 * Proceed to the next multi-letter extension or the end of the
172 while (isa[idx] != '_' && idx < len) {
180 parse_ext_x(struct cpu_desc *desc __unused, char *isa, int idx, int len)
183 * Proceed to the next multi-letter extension or the end of the
186 while (isa[idx] != '_' && idx < len) {
194 parse_ext_z(struct cpu_desc *desc __unused, char *isa, int idx, int len)
197 * Proceed to the next multi-letter extension or the end of the
200 * TODO: parse some of these.
202 while (isa[idx] != '_' && idx < len) {
210 parse_ext_version(char *isa, int idx, u_int *majorp __unused,
211 u_int *minorp __unused)
214 while (isdigit(isa[idx]))
223 while (isdigit(isa[idx]))
230 * Parse the ISA string, building up the set of HWCAP bits as they are found.
233 parse_riscv_isa(struct cpu_desc *desc, char *isa, int len)
237 /* Check the string prefix. */
238 if (strncmp(isa, ISA_PREFIX, ISA_PREFIX_LEN) != 0) {
239 printf("%s: Unrecognized ISA string: %s\n", __func__, isa);
252 desc->isa_extensions |= HWCAP_ISA_BIT(isa[i]);
256 desc->isa_extensions |= HWCAP_ISA_G;
261 * XXX: older versions of this string erroneously
262 * indicated supervisor and user mode support as
263 * single-letter extensions. Detect and skip both 's'
266 if (isa[i - 1] != '_' && isa[i + 1] == 'u') {
272 * Supervisor-level extension namespace.
274 i = parse_ext_s(desc, isa, i, len);
278 * Custom extension namespace. For now, we ignore
281 i = parse_ext_x(desc, isa, i, len);
285 * Multi-letter standard extension namespace.
287 i = parse_ext_z(desc, isa, i, len);
293 /* Unrecognized/unsupported. */
298 i = parse_ext_version(isa, i, NULL, NULL);
306 parse_mmu_fdt(struct cpu_desc *desc, phandle_t node)
310 desc->mmu_caps |= MMU_SV39;
311 if (OF_getprop(node, "mmu-type", mmu, sizeof(mmu)) > 0) {
312 if (strcmp(mmu, "riscv,sv48") == 0)
313 desc->mmu_caps |= MMU_SV48;
314 else if (strcmp(mmu, "riscv,sv57") == 0)
315 desc->mmu_caps |= MMU_SV48 | MMU_SV57;
320 identify_cpu_features_fdt(u_int cpu, struct cpu_desc *desc)
328 node = OF_finddevice("/cpus");
330 printf("%s: could not find /cpus node in FDT\n", __func__);
334 hart = pcpu_find(cpu)->pc_hart;
337 * Locate our current CPU's node in the device-tree, and parse its
338 * contents to detect supported CPU/ISA features and extensions.
340 for (node = OF_child(node); node > 0; node = OF_peer(node)) {
341 /* Skip any non-CPU nodes, such as cpu-map. */
342 if (!ofw_bus_node_is_compatible(node, "riscv"))
346 if (OF_getencprop(node, "reg", ®, sizeof(reg)) <= 0 ||
350 len = OF_getprop(node, "riscv,isa", isa, sizeof(isa));
351 KASSERT(len <= sizeof(isa), ("ISA string truncated"));
353 printf("%s: could not find 'riscv,isa' property "
354 "for CPU %d, hart %u\n", __func__, cpu, hart);
359 * The string is specified to be lowercase, but let's be
362 for (int i = 0; i < len; i++)
363 isa[i] = tolower(isa[i]);
364 if (parse_riscv_isa(desc, isa, len) != 0)
367 /* Check MMU features. */
368 parse_mmu_fdt(desc, node);
374 printf("%s: could not find FDT node for CPU %u, hart %u\n",
375 __func__, cpu, hart);
381 identify_cpu_features(u_int cpu, struct cpu_desc *desc)
384 identify_cpu_features_fdt(cpu, desc);
389 * Update kernel/user global state based on the feature parsing results, stored
392 * We keep only the subset of values common to all CPUs.
395 update_global_capabilities(u_int cpu, struct cpu_desc *desc)
397 #define UPDATE_CAP(t, v) \
406 /* Update the capabilities exposed to userspace via AT_HWCAP. */
407 UPDATE_CAP(elf_hwcap, (u_long)desc->isa_extensions);
410 * MMU capabilities, e.g. Sv48.
412 UPDATE_CAP(mmu_caps, desc->mmu_caps);
414 /* Supervisor-mode extension support. */
415 UPDATE_CAP(has_sstc, (desc->smode_extensions & SV_SSTC) != 0);
416 UPDATE_CAP(has_sscofpmf, (desc->smode_extensions & SV_SSCOFPMF) != 0);
422 identify_cpu_ids(struct cpu_desc *desc)
424 const struct marchid_entry *table = NULL;
427 desc->cpu_mvendor_name = "Unknown";
428 desc->cpu_march_name = "Unknown";
431 * Search for a recognized vendor, and possibly obtain the secondary
432 * table for marchid lookup.
434 for (i = 0; i < nitems(mvendor_ids); i++) {
435 if (mvendorid == mvendor_ids[i].mvendor_id) {
436 desc->cpu_mvendor_name = mvendor_ids[i].mvendor_name;
437 table = mvendor_ids[i].marchid_table;
442 if (marchid == MARCHID_UNIMPL) {
443 desc->cpu_march_name = "Unspecified";
447 if (MARCHID_IS_OPENSOURCE(marchid)) {
448 table = global_marchids;
449 } else if (table == NULL)
452 for (i = 0; table[i].march_name != NULL; i++) {
453 if (marchid == table[i].march_id) {
454 desc->cpu_march_name = table[i].march_name;
461 identify_cpu(u_int cpu)
463 struct cpu_desc *desc = &cpu_desc[cpu];
465 identify_cpu_ids(desc);
466 identify_cpu_features(cpu, desc);
468 update_global_capabilities(cpu, desc);
472 printcpuinfo(u_int cpu)
474 struct cpu_desc *desc;
477 desc = &cpu_desc[cpu];
478 hart = pcpu_find(cpu)->pc_hart;
480 /* XXX: check this here so we are guaranteed to have console output. */
481 KASSERT(desc->isa_extensions != 0,
482 ("Empty extension set for CPU %u, did parsing fail?", cpu));
485 * Suppress the output of some fields in the common case of identical
488 #define SHOULD_PRINT(_field) \
489 (cpu == 0 || desc[0]._field != desc[-1]._field)
491 /* Always print summary line. */
492 printf("CPU %-3u: Vendor=%s Core=%s (Hart %u)\n", cpu,
493 desc->cpu_mvendor_name, desc->cpu_march_name, hart);
495 /* These values are global. */
497 printf(" marchid=%#lx, mimpid=%#lx\n", marchid, mimpid);
499 if (SHOULD_PRINT(mmu_caps)) {
500 printf(" MMU: %#b\n", desc->mmu_caps,
507 if (SHOULD_PRINT(isa_extensions)) {
508 printf(" ISA: %#b\n", desc->isa_extensions,
517 if (SHOULD_PRINT(smode_extensions)) {
518 printf(" S-mode Extensions: %#b\n", desc->smode_extensions,