2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include "opt_platform.h"
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/ctype.h>
43 #include <sys/kernel.h>
45 #include <sys/sysctl.h>
47 #include <machine/cpu.h>
48 #include <machine/cpufunc.h>
49 #include <machine/elf.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
54 #include <dev/fdt/fdt_common.h>
55 #include <dev/ofw/openfirm.h>
56 #include <dev/ofw/ofw_bus_subr.h>
59 char machine[] = "riscv";
61 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0,
64 /* Hardware implementation info. These values may be empty. */
65 register_t mvendorid; /* The CPU's JEDEC vendor ID */
66 register_t marchid; /* The architecture ID */
67 register_t mimpid; /* The implementation ID */
72 const char *cpu_impl_name;
73 const char *cpu_part_name;
76 struct cpu_desc cpu_desc[MAXCPU];
80 const char *part_name;
82 #define CPU_PART_NONE { -1, "Unknown Processor" }
84 struct cpu_implementers {
86 const char *impl_name;
88 #define CPU_IMPLEMENTER_NONE { 0, "Unknown Implementer" }
93 static const struct cpu_parts cpu_parts_std[] = {
94 { CPU_PART_RV32, "RV32" },
95 { CPU_PART_RV64, "RV64" },
96 { CPU_PART_RV128, "RV128" },
101 * Implementers table.
103 const struct cpu_implementers cpu_implementers[] = {
104 { CPU_IMPL_UCB_ROCKET, "UC Berkeley Rocket" },
105 CPU_IMPLEMENTER_NONE,
109 * The ISA string describes the complete set of instructions supported by a
110 * RISC-V CPU. The string begins with a small prefix (e.g. rv64) indicating the
111 * base ISA. It is followed first by single-letter ISA extensions, and then
112 * multi-letter ISA extensions.
114 * Underscores are used mainly to separate consecutive multi-letter extensions,
115 * but may optionally appear between any two extensions. An extension may be
116 * followed by a version number, in the form of 'Mpm', where M is the
117 * extension's major version number, and 'm' is the minor version number.
119 * The format is described in detail by the "ISA Extension Naming Conventions"
120 * chapter of the unprivileged spec.
122 #define ISA_PREFIX ("rv" __XSTRING(__riscv_xlen))
123 #define ISA_PREFIX_LEN (sizeof(ISA_PREFIX) - 1)
126 parse_ext_s(char *isa, int idx, int len)
129 * Proceed to the next multi-letter extension or the end of the
132 * TODO: parse these once we gain support
134 while (isa[idx] != '_' && idx < len) {
142 parse_ext_x(char *isa, int idx, int len)
145 * Proceed to the next multi-letter extension or the end of the
148 while (isa[idx] != '_' && idx < len) {
156 parse_ext_z(char *isa, int idx, int len)
159 * Proceed to the next multi-letter extension or the end of the
162 * TODO: parse some of these.
164 while (isa[idx] != '_' && idx < len) {
172 parse_ext_version(char *isa, int idx, u_int *majorp __unused,
173 u_int *minorp __unused)
176 while (isdigit(isa[idx]))
185 while (isdigit(isa[idx]))
192 * Parse the ISA string, building up the set of HWCAP bits as they are found.
195 parse_riscv_isa(char *isa, int len, u_long *hwcapp)
212 hwcap |= HWCAP_ISA_BIT(isa[i]);
216 hwcap |= HWCAP_ISA_G;
221 * XXX: older versions of this string erroneously
222 * indicated supervisor and user mode support as
223 * single-letter extensions. Detect and skip both 's'
226 if (isa[i - 1] != '_' && isa[i + 1] == 'u') {
232 * Supervisor-level extension namespace.
234 i = parse_ext_s(isa, i, len);
238 * Custom extension namespace. For now, we ignore
241 i = parse_ext_x(isa, i, len);
245 * Multi-letter standard extension namespace.
247 i = parse_ext_z(isa, i, len);
253 /* Unrecognized/unsupported. */
258 i = parse_ext_version(isa, i, NULL, NULL);
267 fill_elf_hwcap(void *dummy __unused)
274 node = OF_finddevice("/cpus");
277 printf("fill_elf_hwcap: Can't find cpus node\n");
282 * Iterate through the CPUs and examine their ISA string. While we
283 * could assign elf_hwcap to be whatever the boot CPU supports, to
284 * handle the (unusual) case of running a system with hetergeneous
285 * ISAs, keep only the extension bits that are common to all harts.
287 for (node = OF_child(node); node > 0; node = OF_peer(node)) {
288 /* Skip any non-CPU nodes, such as cpu-map. */
289 if (!ofw_bus_node_is_compatible(node, "riscv"))
292 len = OF_getprop(node, "riscv,isa", isa, sizeof(isa));
293 KASSERT(len <= sizeof(isa), ("ISA string truncated"));
296 printf("fill_elf_hwcap: "
297 "Can't find riscv,isa property\n");
299 } else if (strncmp(isa, ISA_PREFIX, ISA_PREFIX_LEN) != 0) {
301 printf("fill_elf_hwcap: "
302 "Unsupported ISA string: %s\n", isa);
307 * The string is specified to be lowercase, but let's be
310 for (int i = 0; i < len; i++)
311 isa[i] = tolower(isa[i]);
312 parse_riscv_isa(isa, len, &hwcap);
321 SYSINIT(identcpu, SI_SUB_CPU, SI_ORDER_ANY, fill_elf_hwcap, NULL);
327 const struct cpu_parts *cpu_partsp;
336 /* TODO: can we get misa somewhere ? */
339 cpu = PCPU_GET(cpuid);
341 impl_id = CPU_IMPL(mimpid);
342 for (i = 0; i < nitems(cpu_implementers); i++) {
343 if (impl_id == cpu_implementers[i].impl_id ||
344 cpu_implementers[i].impl_id == 0) {
345 cpu_desc[cpu].cpu_impl = impl_id;
346 cpu_desc[cpu].cpu_impl_name = cpu_implementers[i].impl_name;
347 cpu_partsp = cpu_parts_std;
352 part_id = CPU_PART(misa);
353 for (i = 0; &cpu_partsp[i] != NULL; i++) {
354 if (part_id == cpu_partsp[i].part_id ||
355 cpu_partsp[i].part_id == -1) {
356 cpu_desc[cpu].cpu_part_num = part_id;
357 cpu_desc[cpu].cpu_part_name = cpu_partsp[i].part_name;
362 /* Print details for boot CPU or if we want verbose output */
363 if (cpu == 0 || bootverbose) {
364 printf("CPU(%d): %s %s\n", cpu,
365 cpu_desc[cpu].cpu_impl_name,
366 cpu_desc[cpu].cpu_part_name);