2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/cpuset.h>
45 #include <sys/interrupt.h>
48 #include <machine/bus.h>
49 #include <machine/clock.h>
50 #include <machine/cpu.h>
51 #include <machine/cpufunc.h>
52 #include <machine/frame.h>
53 #include <machine/intr.h>
54 #include <machine/sbi.h>
56 #include <dev/ofw/openfirm.h>
57 #include <dev/ofw/ofw_bus.h>
58 #include <dev/ofw/ofw_bus_subr.h>
61 #include <machine/smp.h>
64 void intr_irq_handler(struct trapframe *tf);
67 struct intr_irqsrc isrc;
71 struct intc_irqsrc isrcs[INTC_NIRQS];
74 riscv_mask_irq(void *source)
78 irq = (uintptr_t)source;
81 case IRQ_TIMER_SUPERVISOR:
82 csr_clear(sie, SIE_STIE);
84 case IRQ_SOFTWARE_USER:
85 csr_clear(sie, SIE_USIE);
87 case IRQ_SOFTWARE_SUPERVISOR:
88 csr_clear(sie, SIE_SSIE);
91 panic("Unknown irq %d\n", irq);
96 riscv_unmask_irq(void *source)
100 irq = (uintptr_t)source;
103 case IRQ_TIMER_SUPERVISOR:
104 csr_set(sie, SIE_STIE);
106 case IRQ_SOFTWARE_USER:
107 csr_set(sie, SIE_USIE);
109 case IRQ_SOFTWARE_SUPERVISOR:
110 csr_set(sie, SIE_SSIE);
113 panic("Unknown irq %d\n", irq);
118 riscv_setup_intr(const char *name, driver_filter_t *filt,
119 void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
121 struct intr_irqsrc *isrc;
124 if (irq < 0 || irq >= INTC_NIRQS)
125 panic("%s: unknown intr %d", __func__, irq);
127 isrc = &isrcs[irq].isrc;
128 if (isrc->isrc_event == NULL) {
129 error = intr_event_create(&isrc->isrc_event, isrc, 0, irq,
130 riscv_mask_irq, riscv_unmask_irq, NULL, NULL, "int%d", irq);
133 riscv_unmask_irq((void*)(uintptr_t)irq);
136 error = intr_event_add_handler(isrc->isrc_event, name,
137 filt, handler, arg, intr_priority(flags), flags, cookiep);
139 printf("Failed to setup intr: %d\n", irq);
147 riscv_teardown_intr(void *ih)
156 riscv_cpu_intr(struct trapframe *frame)
158 struct intr_irqsrc *isrc;
163 KASSERT(frame->tf_scause & EXCP_INTR,
164 ("riscv_cpu_intr: wrong frame passed"));
166 active_irq = (frame->tf_scause & EXCP_MASK);
168 switch (active_irq) {
169 case IRQ_SOFTWARE_USER:
170 case IRQ_SOFTWARE_SUPERVISOR:
171 case IRQ_TIMER_SUPERVISOR:
172 isrc = &isrcs[active_irq].isrc;
173 if (intr_isrc_dispatch(isrc, frame) != 0)
174 printf("stray interrupt %d\n", active_irq);
176 case IRQ_EXTERNAL_SUPERVISOR:
177 intr_irq_handler(frame);
188 riscv_setup_ipihandler(driver_filter_t *filt)
191 riscv_setup_intr("ipi", filt, NULL, NULL, IRQ_SOFTWARE_SUPERVISOR,
192 INTR_TYPE_MISC, NULL);
196 riscv_unmask_ipi(void)
199 csr_set(sie, SIE_SSIE);
204 ipi_send(struct pcpu *pc, int ipi)
208 CTR3(KTR_SMP, "%s: cpu=%d, ipi=%x", __func__, pc->pc_cpuid, ipi);
210 atomic_set_32(&pc->pc_pending_ipis, ipi);
211 mask = (1 << pc->pc_hart);
215 CTR1(KTR_SMP, "%s: sent", __func__);
219 ipi_all_but_self(u_int ipi)
223 other_cpus = all_cpus;
224 CPU_CLR(PCPU_GET(cpuid), &other_cpus);
226 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
227 ipi_selected(other_cpus, ipi);
231 ipi_cpu(int cpu, u_int ipi)
238 CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x\n", __func__, cpu, ipi);
239 ipi_send(cpuid_to_pcpu[cpu], ipi);
243 ipi_selected(cpuset_t cpus, u_int ipi)
248 CTR1(KTR_SMP, "ipi_selected: ipi: %x", ipi);
251 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
252 if (CPU_ISSET(pc->pc_cpuid, &cpus)) {
253 CTR3(KTR_SMP, "%s: pc: %p, ipi: %x\n", __func__, pc,
255 atomic_set_32(&pc->pc_pending_ipis, ipi);
256 mask |= (1 << pc->pc_hart);
263 /* Interrupt machdep initialization routine. */
265 intc_init(void *dummy __unused)
270 for (i = 0; i < INTC_NIRQS; i++) {
272 error = intr_isrc_register(&isrcs[i].isrc, NULL,
275 printf("Can't register interrupt %d\n", i);
279 SYSINIT(intc_init, SI_SUB_INTR, SI_ORDER_MIDDLE, intc_init, NULL);