2 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include <sys/syscall.h>
40 #include <machine/asm.h>
41 #include <machine/param.h>
42 #include <machine/trap.h>
43 #include <machine/riscvreg.h>
44 #include <machine/pte.h>
47 .set kernbase, KERNBASE
56 /* Get the physical address kernel loaded to */
61 sub s9, t2, t1 /* s9 = physmem base */
68 /* Pick a hart to run the boot process. */
71 amoadd.w t0, t1, 0(t0)
74 * We must jump to mpentry in the non-BSP case because the offset is
75 * too large to fit in a 12-bit branch immediate.
84 /* Add L1 entry for kernel */
86 la s2, pagetable_l2 /* Link to next level PN */
87 srli s2, s2, PAGE_SHIFT
90 srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
91 andi a5, a5, 0x1ff /* & 0x1ff */
93 slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
96 /* Store L1 PTE entry to position */
102 /* Level 2 superpages (512 x 2MiB) */
104 srli t4, s9, 21 /* Div physmem base by 2 MiB */
105 li t2, 512 /* Build 512 entries */
109 li t0, (PTE_KERN | PTE_X)
110 slli t2, t4, PTE_PPN1_S /* << PTE_PPN1_S */
112 sd t5, (s1) /* Store PTE entry to position */
113 addi s1, s1, PTE_SIZE
118 /* Create an L1 page for early devmap */
120 la s2, pagetable_l2_devmap /* Link to next level PN */
121 srli s2, s2, PAGE_SHIFT
123 li a5, (VM_MAX_KERNEL_ADDRESS - L2_SIZE)
124 srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
125 andi a5, a5, 0x1ff /* & 0x1ff */
127 slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
130 /* Store single level1 PTE entry to position */
136 /* Create an L2 page superpage for DTB */
137 la s1, pagetable_l2_devmap
139 srli s2, s2, PAGE_SHIFT
142 slli t2, s2, PTE_PPN0_S /* << PTE_PPN0_S */
145 /* Store PTE entry to position */
152 /* Page tables END */
154 /* Setup supervisor trap vector */
161 /* Set page tables base register */
163 srli s2, s2, PAGE_SHIFT
164 li t0, SATP_MODE_SV39
172 /* Setup supervisor trap vector */
173 la t0, cpu_exception_handler
176 /* Ensure sscratch is zero */
180 /* Set the global pointer */
183 la gp, __global_pointer$
186 /* Initialize stack pointer */
190 /* Allocate space for thread0 PCB and riscv_bootparams */
191 addi sp, sp, -(PCB_SIZE + RISCV_BOOTPARAMS_SIZE) & ~STACKALIGNBYTES
194 la s0, _C_LABEL(__bss_start)
195 la s1, _C_LABEL(_end)
202 /* Store boot hart id. */
207 /* Fill riscv_bootparams */
209 sd t0, 0(sp) /* kern_l1pt */
210 sd s9, 8(sp) /* kern_phys */
213 sd t0, 16(sp) /* kern_stack */
215 li t0, (VM_MAX_KERNEL_ADDRESS - 2 * L2_SIZE)
216 sd t0, 24(sp) /* dtbp_virt */
217 sd a1, 32(sp) /* dtbp_phys */
220 call _C_LABEL(initriscv) /* Off we go */
221 call _C_LABEL(mi_startup)
225 .space (PAGE_SIZE * KSTACK_PAGES)
236 /* sigreturn failed, exit */
242 /* This may be copied to the stack, keep it 16-byte aligned */
250 .quad esigcode - sigcode
268 .quad pagetable_l2 /* XXX: Keep page tables VA */
278 * mpentry(unsigned long)
280 * Called by a core when it is being brought online.
284 * Calculate the offset to __riscv_boot_ap
285 * for the current core, cpuid is in a0.
289 /* Get the pointer */
290 la t0, __riscv_boot_ap
294 /* Wait the kernel to be ready */
298 /* Setup stack pointer */
299 la t0, secondary_stacks
300 li t1, (PAGE_SIZE * KSTACK_PAGES)
308 /* Setup supervisor trap vector */
315 /* Set page tables base register */
317 srli s2, s2, PAGE_SHIFT
318 li t0, SATP_MODE_SV39
325 /* Setup supervisor trap vector */
326 la t0, cpu_exception_handler
329 /* Ensure sscratch is zero */
333 /* Set the global pointer */
336 la gp, __global_pointer$