2 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include <sys/syscall.h>
40 #include <machine/asm.h>
41 #include <machine/param.h>
42 #include <machine/trap.h>
43 #include <machine/riscvreg.h>
44 #include <machine/pte.h>
47 .set kernbase, KERNBASE
56 /* Set the global pointer */
59 lla gp, __global_pointer$
62 /* Get the physical address kernel loaded to */
67 sub s9, t2, t1 /* s9 = physmem base */
74 /* Pick a hart to run the boot process. */
77 amoadd.w t0, t1, 0(t0)
80 * We must jump to mpentry in the non-BSP case because the offset is
81 * too large to fit in a 12-bit branch immediate.
90 /* Add L1 entry for kernel */
92 lla s2, pagetable_l2 /* Link to next level PN */
93 srli s2, s2, PAGE_SHIFT
96 srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
97 andi a5, a5, 0x1ff /* & 0x1ff */
99 slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
102 /* Store L1 PTE entry to position */
108 /* Level 2 superpages (512 x 2MiB) */
110 srli t4, s9, 21 /* Div physmem base by 2 MiB */
111 li t2, 512 /* Build 512 entries */
115 li t0, (PTE_KERN | PTE_X)
116 slli t2, t4, PTE_PPN1_S /* << PTE_PPN1_S */
118 sd t5, (s1) /* Store PTE entry to position */
119 addi s1, s1, PTE_SIZE
124 /* Create an L1 page for early devmap */
126 lla s2, pagetable_l2_devmap /* Link to next level PN */
127 srli s2, s2, PAGE_SHIFT
129 li a5, (VM_MAX_KERNEL_ADDRESS - L2_SIZE)
130 srli a5, a5, L1_SHIFT /* >> L1_SHIFT */
131 andi a5, a5, 0x1ff /* & 0x1ff */
133 slli t5, s2, PTE_PPN0_S /* (s2 << PTE_PPN0_S) */
136 /* Store single level1 PTE entry to position */
142 /* Create an L2 page superpage for DTB */
143 lla s1, pagetable_l2_devmap
145 srli s2, s2, PAGE_SHIFT
148 slli t2, s2, PTE_PPN0_S /* << PTE_PPN0_S */
151 /* Store PTE entry to position */
158 /* Page tables END */
160 /* Setup supervisor trap vector */
167 /* Set page tables base register */
169 srli s2, s2, PAGE_SHIFT
170 li t0, SATP_MODE_SV39
177 /* Set the global pointer again, this time with the virtual address. */
180 lla gp, __global_pointer$
183 /* Setup supervisor trap vector */
184 la t0, cpu_exception_handler
187 /* Ensure sscratch is zero */
191 /* Initialize stack pointer */
195 /* Allocate space for thread0 PCB and riscv_bootparams */
196 addi sp, sp, -(PCB_SIZE + RISCV_BOOTPARAMS_SIZE) & ~STACKALIGNBYTES
199 la s0, _C_LABEL(__bss_start)
200 la s1, _C_LABEL(_end)
207 /* Store boot hart id. */
212 /* Fill riscv_bootparams */
214 sd t0, RISCV_BOOTPARAMS_KERN_L1PT(sp)
215 sd s9, RISCV_BOOTPARAMS_KERN_PHYS(sp)
218 sd t0, RISCV_BOOTPARAMS_KERN_STACK(sp)
220 li t0, (VM_MAX_KERNEL_ADDRESS - 2 * L2_SIZE)
221 sd t0, RISCV_BOOTPARAMS_DTBP_VIRT(sp)
222 sd a1, RISCV_BOOTPARAMS_DTBP_PHYS(sp)
225 call _C_LABEL(initriscv) /* Off we go */
226 call _C_LABEL(mi_startup)
230 .space (PAGE_SIZE * KSTACK_PAGES)
241 /* sigreturn failed, exit */
247 /* This may be copied to the stack, keep it 16-byte aligned */
255 .quad esigcode - sigcode
273 .quad pagetable_l2 /* XXX: Keep page tables VA */
283 * mpentry(unsigned long)
285 * Called by a core when it is being brought online.
289 * Calculate the offset to __riscv_boot_ap
290 * for the current core, cpuid is in a0.
294 /* Get the pointer */
295 lla t0, __riscv_boot_ap
299 /* Wait the kernel to be ready */
303 /* Setup stack pointer */
304 lla t0, secondary_stacks
305 li t1, (PAGE_SIZE * KSTACK_PAGES)
313 /* Setup supervisor trap vector */
320 /* Set page tables base register */
322 srli s2, s2, PAGE_SHIFT
323 li t0, SATP_MODE_SV39
330 /* Set the global pointer again, this time with the virtual address. */
333 lla gp, __global_pointer$
336 /* Setup supervisor trap vector */
337 la t0, cpu_exception_handler
340 /* Ensure sscratch is zero */