2 * Copyright (c) 2015 The FreeBSD Foundation
3 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
6 * Portions of this software were developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
9 * Portions of this software were developed by SRI International and the
10 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
13 * Portions of this software were developed by the University of Cambridge
14 * Computer Laboratory as part of the CTSRD Project, with support from the
15 * UK Higher Education Innovation Fund (HEIF).
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include "opt_kstack_pages.h"
40 #include "opt_platform.h"
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
55 #include <sys/sched.h>
60 #include <vm/vm_extern.h>
61 #include <vm/vm_kern.h>
62 #include <vm/vm_map.h>
64 #include <machine/intr.h>
65 #include <machine/smp.h>
66 #include <machine/sbi.h>
69 #include <dev/ofw/openfirm.h>
70 #include <dev/ofw/ofw_cpu.h>
73 boolean_t ofw_cpu_reg(phandle_t node, u_int, cell_t *);
75 uint32_t __riscv_boot_ap[MAXCPU];
84 static device_identify_t riscv64_cpu_identify;
85 static device_probe_t riscv64_cpu_probe;
86 static device_attach_t riscv64_cpu_attach;
88 static int ipi_handler(void *);
90 struct mtx ap_boot_mtx;
91 struct pcb stoppcbs[MAXCPU];
93 extern uint32_t boot_hart;
94 extern cpuset_t all_harts;
97 static uint32_t cpu_reg[MAXCPU][2];
99 static device_t cpu_list[MAXCPU];
101 void mpentry(unsigned long cpuid);
102 void init_secondary(uint64_t);
104 uint8_t secondary_stacks[MAXCPU][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
106 /* Set to 1 once we're ready to let the APs out of the pen. */
107 volatile int aps_ready = 0;
109 /* Temporary variables for init_secondary() */
110 void *dpcpu[MAXCPU - 1];
112 static device_method_t riscv64_cpu_methods[] = {
113 /* Device interface */
114 DEVMETHOD(device_identify, riscv64_cpu_identify),
115 DEVMETHOD(device_probe, riscv64_cpu_probe),
116 DEVMETHOD(device_attach, riscv64_cpu_attach),
121 static devclass_t riscv64_cpu_devclass;
122 static driver_t riscv64_cpu_driver = {
128 DRIVER_MODULE(riscv64_cpu, cpu, riscv64_cpu_driver, riscv64_cpu_devclass, 0, 0);
131 riscv64_cpu_identify(driver_t *driver, device_t parent)
134 if (device_find_child(parent, "riscv64_cpu", -1) != NULL)
136 if (BUS_ADD_CHILD(parent, 0, "riscv64_cpu", -1) == NULL)
137 device_printf(parent, "add child failed\n");
141 riscv64_cpu_probe(device_t dev)
145 cpuid = device_get_unit(dev);
146 if (cpuid >= MAXCPU || cpuid > mp_maxid)
154 riscv64_cpu_attach(device_t dev)
161 cpuid = device_get_unit(dev);
163 if (cpuid >= MAXCPU || cpuid > mp_maxid)
165 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
167 reg = cpu_get_cpuid(dev, ®_size);
172 device_printf(dev, "register <");
173 for (i = 0; i < reg_size; i++)
174 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
178 /* Set the device to start it later */
179 cpu_list[cpuid] = dev;
185 release_aps(void *dummy __unused)
193 /* Setup the IPI handler */
194 riscv_setup_ipihandler(ipi_handler);
196 atomic_store_rel_int(&aps_ready, 1);
198 /* Wake up the other CPUs */
200 CPU_CLR(boot_hart, &mask);
202 printf("Release APs\n");
204 sbi_send_ipi(mask.__bits);
206 for (i = 0; i < 2000; i++) {
208 for (cpu = 0; cpu <= mp_maxid; cpu++) {
217 printf("APs not started\n");
219 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
222 init_secondary(uint64_t hart)
227 /* Renumber this cpu */
229 if (cpuid < boot_hart)
230 cpuid += mp_maxid + 1;
233 /* Setup the pcpu pointer */
234 pcpup = &__pcpu[cpuid];
235 __asm __volatile("mv tp, %0" :: "r"(pcpup));
237 /* Workaround: make sure wfi doesn't halt the hart */
238 csr_set(sie, SIE_SSIE);
239 csr_set(sip, SIE_SSIE);
241 /* Spin until the BSP releases the APs */
243 __asm __volatile("wfi");
245 /* Initialize curthread */
246 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
247 pcpup->pc_curthread = pcpup->pc_idlethread;
248 pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
251 * Identify current CPU. This is necessary to setup
252 * affinity registers and to provide support for
253 * runtime chip identification.
257 /* Enable software interrupts */
260 /* Start per-CPU event timers. */
263 /* Enable external (PLIC) interrupts */
264 csr_set(sie, SIE_SEIE);
266 /* Activate process 0's pmap. */
267 pmap_activate_boot(vmspace_pmap(proc0.p_vmspace));
269 mtx_lock_spin(&ap_boot_mtx);
271 atomic_add_rel_32(&smp_cpus, 1);
273 if (smp_cpus == mp_ncpus) {
274 /* enable IPI's, tlb shootdown, freezes etc */
275 atomic_store_rel_int(&smp_started, 1);
278 mtx_unlock_spin(&ap_boot_mtx);
280 /* Enter the scheduler */
283 panic("scheduler returned us to init_secondary");
288 ipi_handler(void *arg)
296 cpu = PCPU_GET(cpuid);
300 ipi_bitmap = atomic_readandclear_int(PCPU_PTR(pending_ipis));
302 return (FILTER_HANDLED);
304 while ((bit = ffs(ipi_bitmap))) {
313 CTR0(KTR_SMP, "IPI_AST");
316 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
317 sched_preempt(curthread);
320 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
321 smp_rendezvous_action();
325 CTR0(KTR_SMP, (ipi == IPI_STOP) ? "IPI_STOP" : "IPI_STOP_HARD");
326 savectx(&stoppcbs[cpu]);
328 /* Indicate we are stopped */
329 CPU_SET_ATOMIC(cpu, &stopped_cpus);
331 /* Wait for restart */
332 while (!CPU_ISSET(cpu, &started_cpus))
335 CPU_CLR_ATOMIC(cpu, &started_cpus);
336 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
337 CTR0(KTR_SMP, "IPI_STOP (restart)");
340 * The kernel debugger might have set a breakpoint,
341 * so flush the instruction cache.
346 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
350 panic("Unknown IPI %#0x on cpu %d", ipi, curcpu);
354 return (FILTER_HANDLED);
361 return (smp_topo_none());
364 /* Determine if we running MP machine */
369 return (mp_ncpus > 1);
374 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
380 /* Check if this hart supports MMU. */
381 if (OF_getproplen(node, "mmu-type") < 0)
384 KASSERT(id < MAXCPU, ("Too many CPUs"));
386 KASSERT(addr_size == 1 || addr_size == 2, ("Invalid register size"));
388 cpu_reg[id][0] = reg[0];
390 cpu_reg[id][1] = reg[1];
394 if (addr_size == 2) {
399 KASSERT(hart < MAXCPU, ("Too many harts."));
401 /* We are already running on this cpu */
402 if (hart == boot_hart)
406 * Rotate the CPU IDs to put the boot CPU as CPU 0.
407 * We keep the other CPUs ordered.
410 if (cpuid < boot_hart)
411 cpuid += mp_maxid + 1;
414 /* Check if we are able to start this cpu */
415 if (cpuid > mp_maxid)
418 pcpup = &__pcpu[cpuid];
419 pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
420 pcpup->pc_hart = hart;
422 dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
423 dpcpu_init(dpcpu[cpuid - 1], cpuid);
425 printf("Starting CPU %u (hart %lx)\n", cpuid, hart);
426 __riscv_boot_ap[hart] = 1;
428 CPU_SET(cpuid, &all_cpus);
429 CPU_SET(hart, &all_harts);
435 /* Initialize and fire up non-boot processors */
440 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
442 CPU_SET(0, &all_cpus);
443 CPU_SET(boot_hart, &all_harts);
445 switch(cpu_enum_method) {
448 ofw_cpu_early_foreach(cpu_init_fdt, true);
456 /* Introduce rest of cores to the world */
458 cpu_mp_announce(void)
463 cpu_check_mmu(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
466 /* Check if this hart supports MMU. */
467 if (OF_getproplen(node, "mmu-type") < 0)
474 cpu_mp_setmaxid(void)
479 cores = ofw_cpu_early_foreach(cpu_check_mmu, true);
481 cores = MIN(cores, MAXCPU);
483 printf("Found %d CPUs in the device tree\n", cores);
485 mp_maxid = cores - 1;
486 cpu_enum_method = CPUS_FDT;
492 printf("No CPU data, limiting to 1 core\n");