2 * Copyright (c) 2015 The FreeBSD Foundation
3 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
6 * Portions of this software were developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
9 * Portions of this software were developed by SRI International and the
10 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
13 * Portions of this software were developed by the University of Cambridge
14 * Computer Laboratory as part of the CTSRD Project, with support from the
15 * UK Higher Education Innovation Fund (HEIF).
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include "opt_kstack_pages.h"
40 #include "opt_platform.h"
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
45 #include <sys/param.h>
46 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
54 #include <sys/sched.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_kern.h>
62 #include <machine/intr.h>
63 #include <machine/smp.h>
64 #include <machine/sbi.h>
67 #include <dev/ofw/openfirm.h>
68 #include <dev/ofw/ofw_cpu.h>
71 boolean_t ofw_cpu_reg(phandle_t node, u_int, cell_t *);
73 extern struct pcpu __pcpu[];
75 uint32_t __riscv_boot_ap[MAXCPU];
84 static device_identify_t riscv64_cpu_identify;
85 static device_probe_t riscv64_cpu_probe;
86 static device_attach_t riscv64_cpu_attach;
88 static int ipi_handler(void *);
90 struct mtx ap_boot_mtx;
91 struct pcb stoppcbs[MAXCPU];
94 static uint32_t cpu_reg[MAXCPU][2];
96 static device_t cpu_list[MAXCPU];
98 void mpentry(unsigned long cpuid);
99 void init_secondary(uint64_t);
101 uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
103 /* Set to 1 once we're ready to let the APs out of the pen. */
104 volatile int aps_ready = 0;
106 /* Temporary variables for init_secondary() */
107 void *dpcpu[MAXCPU - 1];
109 static device_method_t riscv64_cpu_methods[] = {
110 /* Device interface */
111 DEVMETHOD(device_identify, riscv64_cpu_identify),
112 DEVMETHOD(device_probe, riscv64_cpu_probe),
113 DEVMETHOD(device_attach, riscv64_cpu_attach),
118 static devclass_t riscv64_cpu_devclass;
119 static driver_t riscv64_cpu_driver = {
125 DRIVER_MODULE(riscv64_cpu, cpu, riscv64_cpu_driver, riscv64_cpu_devclass, 0, 0);
128 riscv64_cpu_identify(driver_t *driver, device_t parent)
131 if (device_find_child(parent, "riscv64_cpu", -1) != NULL)
133 if (BUS_ADD_CHILD(parent, 0, "riscv64_cpu", -1) == NULL)
134 device_printf(parent, "add child failed\n");
138 riscv64_cpu_probe(device_t dev)
142 cpuid = device_get_unit(dev);
143 if (cpuid >= MAXCPU || cpuid > mp_maxid)
151 riscv64_cpu_attach(device_t dev)
158 cpuid = device_get_unit(dev);
160 if (cpuid >= MAXCPU || cpuid > mp_maxid)
162 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
164 reg = cpu_get_cpuid(dev, ®_size);
169 device_printf(dev, "register <");
170 for (i = 0; i < reg_size; i++)
171 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
175 /* Set the device to start it later */
176 cpu_list[cpuid] = dev;
182 release_aps(void *dummy __unused)
190 /* Setup the IPI handler */
191 riscv_setup_ipihandler(ipi_handler);
193 atomic_store_rel_int(&aps_ready, 1);
195 /* Wake up the other CPUs */
198 for (i = 1; i < mp_ncpus; i++)
203 printf("Release APs\n");
205 for (i = 0; i < 2000; i++) {
207 for (cpu = 0; cpu <= mp_maxid; cpu++) {
216 printf("APs not started\n");
218 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
221 init_secondary(uint64_t cpu)
225 /* Setup the pcpu pointer */
226 pcpup = &__pcpu[cpu];
227 __asm __volatile("mv gp, %0" :: "r"(pcpup));
229 /* Workaround: make sure wfi doesn't halt the hart */
230 csr_set(sie, SIE_SSIE);
231 csr_set(sip, SIE_SSIE);
233 /* Spin until the BSP releases the APs */
235 __asm __volatile("wfi");
237 /* Initialize curthread */
238 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
239 pcpup->pc_curthread = pcpup->pc_idlethread;
240 pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
243 * Identify current CPU. This is necessary to setup
244 * affinity registers and to provide support for
245 * runtime chip identification.
249 /* Enable software interrupts */
252 /* Start per-CPU event timers. */
255 /* Enable external (PLIC) interrupts */
256 csr_set(sie, SIE_SEIE);
258 mtx_lock_spin(&ap_boot_mtx);
260 atomic_add_rel_32(&smp_cpus, 1);
262 if (smp_cpus == mp_ncpus) {
263 /* enable IPI's, tlb shootdown, freezes etc */
264 atomic_store_rel_int(&smp_started, 1);
267 mtx_unlock_spin(&ap_boot_mtx);
269 /* Enter the scheduler */
272 panic("scheduler returned us to init_secondary");
277 ipi_handler(void *arg)
285 cpu = PCPU_GET(cpuid);
289 ipi_bitmap = atomic_readandclear_int(PCPU_PTR(pending_ipis));
291 return (FILTER_HANDLED);
293 while ((bit = ffs(ipi_bitmap))) {
302 CTR0(KTR_SMP, "IPI_AST");
305 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
306 sched_preempt(curthread);
309 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
310 smp_rendezvous_action();
314 CTR0(KTR_SMP, (ipi == IPI_STOP) ? "IPI_STOP" : "IPI_STOP_HARD");
315 savectx(&stoppcbs[cpu]);
317 /* Indicate we are stopped */
318 CPU_SET_ATOMIC(cpu, &stopped_cpus);
320 /* Wait for restart */
321 while (!CPU_ISSET(cpu, &started_cpus))
324 CPU_CLR_ATOMIC(cpu, &started_cpus);
325 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
326 CTR0(KTR_SMP, "IPI_STOP (restart)");
329 * The kernel debugger might have set a breakpoint,
330 * so flush the instruction cache.
335 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
339 panic("Unknown IPI %#0x on cpu %d", ipi, curcpu);
343 return (FILTER_HANDLED);
350 return (smp_topo_none());
353 /* Determine if we running MP machine */
358 return (mp_ncpus > 1);
363 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
368 /* Check we are able to start this cpu */
372 KASSERT(id < MAXCPU, ("Too many CPUs"));
374 KASSERT(addr_size == 1 || addr_size == 2, ("Invalid register size"));
376 cpu_reg[id][0] = reg[0];
378 cpu_reg[id][1] = reg[1];
382 if (addr_size == 2) {
384 target_cpu |= reg[1];
389 /* We are already running on cpu 0 */
394 pcpu_init(pcpup, id, sizeof(struct pcpu));
396 dpcpu[id - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
397 dpcpu_init(dpcpu[id - 1], id);
399 printf("Starting CPU %u (%lx)\n", id, target_cpu);
400 __riscv_boot_ap[id] = 1;
402 CPU_SET(id, &all_cpus);
408 /* Initialize and fire up non-boot processors */
413 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
415 CPU_SET(0, &all_cpus);
417 switch(cpu_enum_method) {
420 ofw_cpu_early_foreach(cpu_init_fdt, true);
428 /* Introduce rest of cores to the world */
430 cpu_mp_announce(void)
435 cpu_mp_setmaxid(void)
440 cores = ofw_cpu_early_foreach(NULL, false);
442 cores = MIN(cores, MAXCPU);
444 printf("Found %d CPUs in the device tree\n", cores);
446 mp_maxid = cores - 1;
447 cpu_enum_method = CPUS_FDT;
453 printf("No CPU data, limiting to 1 core\n");