sys/riscv/riscv/timer.c

   1 /*-
   2  * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * Portions of this software were developed by SRI International and the
   6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
   7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
   8  *
   9  * Portions of this software were developed by the University of Cambridge
  10  * Computer Laboratory as part of the CTSRD Project, with support from the
  11  * UK Higher Education Innovation Fund (HEIF).
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  * 1. Redistributions of source code must retain the above copyright
  17  *    notice, this list of conditions and the following disclaimer.
  18  * 2. Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 /*
  36  * RISC-V Timer
  37  */
  38
  39 #include "opt_platform.h"
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/bus.h>
  47 #include <sys/kernel.h>
  48 #include <sys/module.h>
  49 #include <sys/malloc.h>
  50 #include <sys/rman.h>
  51 #include <sys/timeet.h>
  52 #include <sys/timetc.h>
  53 #include <sys/watchdog.h>
  54
  55 #include <sys/proc.h>
  56
  57 #include <machine/bus.h>
  58 #include <machine/cpu.h>
  59 #include <machine/intr.h>
  60 #include <machine/asm.h>
  61 #include <machine/trap.h>
  62 #include <machine/sbi.h>
  63
  64 #define DEFAULT_FREQ    10000000
  65
  66 #define TIMER_COUNTS            0x00
  67 #define TIMER_MTIMECMP(cpu)     (cpu * 8)
  68
  69 struct riscv_timer_softc {
  70         void                    *ih;
  71         uint32_t                clkfreq;
  72         struct eventtimer       et;
  73 };
  74
  75 static struct riscv_timer_softc *riscv_timer_sc = NULL;
  76
  77 static timecounter_get_t riscv_timer_get_timecount;
  78
  79 static struct timecounter riscv_timer_timecount = {
  80         .tc_name           = "RISC-V Timecounter",
  81         .tc_get_timecount  = riscv_timer_get_timecount,
  82         .tc_poll_pps       = NULL,
  83         .tc_counter_mask   = ~0u,
  84         .tc_frequency      = 0,
  85         .tc_quality        = 1000,
  86 };
  87
  88 static inline uint64_t
  89 get_cycles(void)
  90 {
  91         uint64_t cycles;
  92
  93         __asm __volatile("rdtime %0" : "=r" (cycles));
  94
  95         return (cycles);
  96 }
  97
  98 static long
  99 get_counts(struct riscv_timer_softc *sc)
 100 {
 101         uint64_t counts;
 102
 103         counts = get_cycles();
 104
 105         return (counts);
 106 }
 107
 108 static unsigned
 109 riscv_timer_get_timecount(struct timecounter *tc)
 110 {
 111         struct riscv_timer_softc *sc;
 112
 113         sc = tc->tc_priv;
 114
 115         return (get_counts(sc));
 116 }
 117
 118 static int
 119 riscv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 120 {
 121         uint64_t counts;
 122
 123         if (first != 0) {
 124                 counts = ((uint32_t)et->et_frequency * first) >> 32;
 125                 sbi_set_timer(get_cycles() + counts);
 126                 csr_set(sie, SIE_STIE);
 127
 128                 return (0);
 129         }
 130
 131         return (EINVAL);
 132
 133 }
 134
 135 static int
 136 riscv_timer_stop(struct eventtimer *et)
 137 {
 138
 139         /* TODO */
 140
 141         return (0);
 142 }
 143
 144 static int
 145 riscv_timer_intr(void *arg)
 146 {
 147         struct riscv_timer_softc *sc;
 148
 149         sc = (struct riscv_timer_softc *)arg;
 150
 151         csr_clear(sip, SIP_STIP);
 152
 153         if (sc->et.et_active)
 154                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 155
 156         return (FILTER_HANDLED);
 157 }
 158
 159 static int
 160 riscv_timer_probe(device_t dev)
 161 {
 162
 163         device_set_desc(dev, "RISC-V Timer");
 164
 165         return (BUS_PROBE_DEFAULT);
 166 }
 167
 168 static int
 169 riscv_timer_attach(device_t dev)
 170 {
 171         struct riscv_timer_softc *sc;
 172         int error;
 173
 174         sc = device_get_softc(dev);
 175         if (riscv_timer_sc)
 176                 return (ENXIO);
 177
 178         if (device_get_unit(dev) != 0)
 179                 return ENXIO;
 180
 181         sc->clkfreq = DEFAULT_FREQ;
 182         if (sc->clkfreq == 0) {
 183                 device_printf(dev, "No clock frequency specified\n");
 184                 return (ENXIO);
 185         }
 186
 187         riscv_timer_sc = sc;
 188
 189         /* Setup IRQs handler */
 190         error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr,
 191             NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih);
 192         if (error) {
 193                 device_printf(dev, "Unable to alloc int resource.\n");
 194                 return (ENXIO);
 195         }
 196
 197         riscv_timer_timecount.tc_frequency = sc->clkfreq;
 198         riscv_timer_timecount.tc_priv = sc;
 199         tc_init(&riscv_timer_timecount);
 200
 201         sc->et.et_name = "RISC-V Eventtimer";
 202         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
 203         sc->et.et_quality = 1000;
 204
 205         sc->et.et_frequency = sc->clkfreq;
 206         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 207         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 208         sc->et.et_start = riscv_timer_start;
 209         sc->et.et_stop = riscv_timer_stop;
 210         sc->et.et_priv = sc;
 211         et_register(&sc->et);
 212
 213         return (0);
 214 }
 215
 216 static device_method_t riscv_timer_methods[] = {
 217         DEVMETHOD(device_probe,         riscv_timer_probe),
 218         DEVMETHOD(device_attach,        riscv_timer_attach),
 219         { 0, 0 }
 220 };
 221
 222 static driver_t riscv_timer_driver = {
 223         "timer",
 224         riscv_timer_methods,
 225         sizeof(struct riscv_timer_softc),
 226 };
 227
 228 static devclass_t riscv_timer_devclass;
 229
 230 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, riscv_timer_devclass,
 231     0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
 232
 233 void
 234 DELAY(int usec)
 235 {
 236         int64_t counts, counts_per_usec;
 237         uint64_t first, last;
 238
 239         /*
 240          * Check the timers are setup, if not just
 241          * use a for loop for the meantime
 242          */
 243         if (riscv_timer_sc == NULL) {
 244                 for (; usec > 0; usec--)
 245                         for (counts = 200; counts > 0; counts--)
 246                                 /*
 247                                  * Prevent the compiler from optimizing
 248                                  * out the loop
 249                                  */
 250                                 cpufunc_nullop();
 251                 return;
 252         }
 253         TSENTER();
 254
 255         /* Get the number of times to count */
 256         counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1);
 257
 258         /*
 259          * Clamp the timeout at a maximum value (about 32 seconds with
 260          * a 66MHz clock). *Nobody* should be delay()ing for anywhere
 261          * near that length of time and if they are, they should be hung
 262          * out to dry.
 263          */
 264         if (usec >= (0x80000000U / counts_per_usec))
 265                 counts = (0x80000000U / counts_per_usec) - 1;
 266         else
 267                 counts = usec * counts_per_usec;
 268
 269         first = get_counts(riscv_timer_sc);
 270
 271         while (counts > 0) {
 272                 last = get_counts(riscv_timer_sc);
 273                 counts -= (int64_t)(last - first);
 274                 first = last;
 275         }
 276         TSEXIT();
 277 }