sys/riscv/riscv/timer.c

   1 /*-
   2  * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * Portions of this software were developed by SRI International and the
   6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
   7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
   8  *
   9  * Portions of this software were developed by the University of Cambridge
  10  * Computer Laboratory as part of the CTSRD Project, with support from the
  11  * UK Higher Education Innovation Fund (HEIF).
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  * 1. Redistributions of source code must retain the above copyright
  17  *    notice, this list of conditions and the following disclaimer.
  18  * 2. Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 /*
  36  * RISC-V Timer
  37  */
  38
  39 #include "opt_platform.h"
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/bus.h>
  47 #include <sys/kernel.h>
  48 #include <sys/module.h>
  49 #include <sys/malloc.h>
  50 #include <sys/rman.h>
  51 #include <sys/timeet.h>
  52 #include <sys/timetc.h>
  53 #include <sys/vdso.h>
  54 #include <sys/watchdog.h>
  55
  56 #include <sys/proc.h>
  57
  58 #include <machine/bus.h>
  59 #include <machine/cpu.h>
  60 #include <machine/cpufunc.h>
  61 #include <machine/intr.h>
  62 #include <machine/asm.h>
  63 #include <machine/trap.h>
  64 #include <machine/sbi.h>
  65
  66 #include <dev/fdt/fdt_common.h>
  67 #include <dev/ofw/ofw_bus.h>
  68 #include <dev/ofw/ofw_bus_subr.h>
  69 #include <dev/ofw/openfirm.h>
  70
  71 #define TIMER_COUNTS            0x00
  72 #define TIMER_MTIMECMP(cpu)     (cpu * 8)
  73
  74 struct riscv_timer_softc {
  75         void                    *ih;
  76         uint32_t                clkfreq;
  77         struct eventtimer       et;
  78 };
  79
  80 static struct riscv_timer_softc *riscv_timer_sc = NULL;
  81
  82 static uint32_t riscv_timer_fill_vdso_timehands(struct vdso_timehands *vdso_th,
  83     struct timecounter *tc);
  84
  85 static timecounter_get_t riscv_timer_get_timecount;
  86
  87 static struct timecounter riscv_timer_timecount = {
  88         .tc_name           = "RISC-V Timecounter",
  89         .tc_get_timecount  = riscv_timer_get_timecount,
  90         .tc_poll_pps       = NULL,
  91         .tc_counter_mask   = ~0u,
  92         .tc_frequency      = 0,
  93         .tc_quality        = 1000,
  94         .tc_fill_vdso_timehands = riscv_timer_fill_vdso_timehands,
  95 };
  96
  97 static inline uint64_t
  98 get_cycles(void)
  99 {
 100
 101         return (rdtime());
 102 }
 103
 104 static long
 105 get_counts(struct riscv_timer_softc *sc)
 106 {
 107         uint64_t counts;
 108
 109         counts = get_cycles();
 110
 111         return (counts);
 112 }
 113
 114 static unsigned
 115 riscv_timer_get_timecount(struct timecounter *tc)
 116 {
 117         struct riscv_timer_softc *sc;
 118
 119         sc = tc->tc_priv;
 120
 121         return (get_counts(sc));
 122 }
 123
 124 static int
 125 riscv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 126 {
 127         uint64_t counts;
 128
 129         if (first != 0) {
 130                 counts = ((uint32_t)et->et_frequency * first) >> 32;
 131                 sbi_set_timer(get_cycles() + counts);
 132                 csr_set(sie, SIE_STIE);
 133
 134                 return (0);
 135         }
 136
 137         return (EINVAL);
 138
 139 }
 140
 141 static int
 142 riscv_timer_stop(struct eventtimer *et)
 143 {
 144
 145         /* Disable timer interrupts. */
 146         csr_clear(sie, SIE_STIE);
 147
 148         return (0);
 149 }
 150
 151 static int
 152 riscv_timer_intr(void *arg)
 153 {
 154         struct riscv_timer_softc *sc;
 155
 156         sc = (struct riscv_timer_softc *)arg;
 157
 158         csr_clear(sip, SIP_STIP);
 159
 160         if (sc->et.et_active)
 161                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 162
 163         return (FILTER_HANDLED);
 164 }
 165
 166 static int
 167 riscv_timer_get_timebase(device_t dev, uint32_t *freq)
 168 {
 169         phandle_t node;
 170         int len;
 171
 172         node = OF_finddevice("/cpus");
 173         if (node == -1) {
 174                 if (bootverbose)
 175                         device_printf(dev, "Can't find cpus node.\n");
 176                 return (ENXIO);
 177         }
 178
 179         len = OF_getproplen(node, "timebase-frequency");
 180         if (len != 4) {
 181                 if (bootverbose)
 182                         device_printf(dev,
 183                             "Can't find timebase-frequency property.\n");
 184                 return (ENXIO);
 185         }
 186
 187         OF_getencprop(node, "timebase-frequency", freq, len);
 188
 189         return (0);
 190 }
 191
 192 static int
 193 riscv_timer_probe(device_t dev)
 194 {
 195
 196         device_set_desc(dev, "RISC-V Timer");
 197
 198         return (BUS_PROBE_DEFAULT);
 199 }
 200
 201 static int
 202 riscv_timer_attach(device_t dev)
 203 {
 204         struct riscv_timer_softc *sc;
 205         int error;
 206
 207         sc = device_get_softc(dev);
 208         if (riscv_timer_sc)
 209                 return (ENXIO);
 210
 211         if (device_get_unit(dev) != 0)
 212                 return (ENXIO);
 213
 214         if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) {
 215                 device_printf(dev, "No clock frequency specified\n");
 216                 return (ENXIO);
 217         }
 218
 219         riscv_timer_sc = sc;
 220
 221         /* Setup IRQs handler */
 222         error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr,
 223             NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih);
 224         if (error) {
 225                 device_printf(dev, "Unable to alloc int resource.\n");
 226                 return (ENXIO);
 227         }
 228
 229         riscv_timer_timecount.tc_frequency = sc->clkfreq;
 230         riscv_timer_timecount.tc_priv = sc;
 231         tc_init(&riscv_timer_timecount);
 232
 233         sc->et.et_name = "RISC-V Eventtimer";
 234         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
 235         sc->et.et_quality = 1000;
 236
 237         sc->et.et_frequency = sc->clkfreq;
 238         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 239         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 240         sc->et.et_start = riscv_timer_start;
 241         sc->et.et_stop = riscv_timer_stop;
 242         sc->et.et_priv = sc;
 243         et_register(&sc->et);
 244
 245         set_cputicker(get_timecount, sc->clkfreq, false);
 246
 247         return (0);
 248 }
 249
 250 static device_method_t riscv_timer_methods[] = {
 251         DEVMETHOD(device_probe,         riscv_timer_probe),
 252         DEVMETHOD(device_attach,        riscv_timer_attach),
 253         { 0, 0 }
 254 };
 255
 256 static driver_t riscv_timer_driver = {
 257         "timer",
 258         riscv_timer_methods,
 259         sizeof(struct riscv_timer_softc),
 260 };
 261
 262 static devclass_t riscv_timer_devclass;
 263
 264 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, riscv_timer_devclass,
 265     0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
 266
 267 void
 268 DELAY(int usec)
 269 {
 270         int64_t counts, counts_per_usec;
 271         uint64_t first, last;
 272
 273         /*
 274          * Check the timers are setup, if not just
 275          * use a for loop for the meantime
 276          */
 277         if (riscv_timer_sc == NULL) {
 278                 for (; usec > 0; usec--)
 279                         for (counts = 200; counts > 0; counts--)
 280                                 /*
 281                                  * Prevent the compiler from optimizing
 282                                  * out the loop
 283                                  */
 284                                 cpufunc_nullop();
 285                 return;
 286         }
 287         TSENTER();
 288
 289         /* Get the number of times to count */
 290         counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1);
 291
 292         /*
 293          * Clamp the timeout at a maximum value (about 32 seconds with
 294          * a 66MHz clock). *Nobody* should be delay()ing for anywhere
 295          * near that length of time and if they are, they should be hung
 296          * out to dry.
 297          */
 298         if (usec >= (0x80000000U / counts_per_usec))
 299                 counts = (0x80000000U / counts_per_usec) - 1;
 300         else
 301                 counts = usec * counts_per_usec;
 302
 303         first = get_counts(riscv_timer_sc);
 304
 305         while (counts > 0) {
 306                 last = get_counts(riscv_timer_sc);
 307                 counts -= (int64_t)(last - first);
 308                 first = last;
 309         }
 310         TSEXIT();
 311 }
 312
 313 static uint32_t
 314 riscv_timer_fill_vdso_timehands(struct vdso_timehands *vdso_th,
 315     struct timecounter *tc)
 316 {
 317         vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME;
 318         bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
 319         return (1);
 320 }