2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include "opt_platform.h"
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/malloc.h>
51 #include <sys/timeet.h>
52 #include <sys/timetc.h>
53 #include <sys/watchdog.h>
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
60 #include <machine/asm.h>
61 #include <machine/trap.h>
62 #include <machine/sbi.h>
64 #include <dev/fdt/fdt_common.h>
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
69 #define DEFAULT_FREQ 1000000
71 #define TIMER_COUNTS 0x00
72 #define TIMER_MTIMECMP(cpu) (0x08 + (cpu * 8))
74 #define READ8(_sc, _reg) \
75 bus_space_read_8(_sc->bst, _sc->bsh, _reg)
76 #define WRITE8(_sc, _reg, _val) \
77 bus_space_write_8(_sc->bst, _sc->bsh, _reg, _val)
79 struct riscv_tmr_softc {
80 struct resource *res[2];
82 bus_space_handle_t bsh;
88 static struct riscv_tmr_softc *riscv_tmr_sc = NULL;
90 static struct resource_spec timer_spec[] = {
91 { SYS_RES_MEMORY, 0, RF_ACTIVE },
92 { SYS_RES_IRQ, 0, RF_ACTIVE },
96 static timecounter_get_t riscv_tmr_get_timecount;
98 static struct timecounter riscv_tmr_timecount = {
99 .tc_name = "RISC-V Timecounter",
100 .tc_get_timecount = riscv_tmr_get_timecount,
102 .tc_counter_mask = ~0u,
108 get_counts(struct riscv_tmr_softc *sc)
111 return (READ8(sc, TIMER_COUNTS));
115 riscv_tmr_get_timecount(struct timecounter *tc)
117 struct riscv_tmr_softc *sc;
121 return (get_counts(sc));
125 riscv_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
127 struct riscv_tmr_softc *sc;
131 sc = (struct riscv_tmr_softc *)et->et_priv;
134 counts = ((uint32_t)et->et_frequency * first) >> 32;
135 counts += READ8(sc, TIMER_COUNTS);
136 cpu = PCPU_GET(cpuid);
137 WRITE8(sc, TIMER_MTIMECMP(cpu), counts);
138 csr_set(sie, SIE_STIE);
139 sbi_set_timer(counts);
149 riscv_tmr_stop(struct eventtimer *et)
151 struct riscv_tmr_softc *sc;
153 sc = (struct riscv_tmr_softc *)et->et_priv;
161 riscv_tmr_intr(void *arg)
163 struct riscv_tmr_softc *sc;
165 sc = (struct riscv_tmr_softc *)arg;
167 csr_clear(sip, SIP_STIP);
169 if (sc->et.et_active)
170 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
172 return (FILTER_HANDLED);
176 riscv_tmr_fdt_probe(device_t dev)
179 if (!ofw_bus_status_okay(dev))
182 if (ofw_bus_is_compatible(dev, "riscv,timer")) {
183 device_set_desc(dev, "RISC-V Timer");
184 return (BUS_PROBE_DEFAULT);
191 riscv_tmr_attach(device_t dev)
193 struct riscv_tmr_softc *sc;
198 sc = device_get_softc(dev);
202 /* Get the base clock frequency */
203 node = ofw_bus_get_node(dev);
205 error = OF_getprop(node, "clock-frequency", &clock,
208 sc->clkfreq = fdt32_to_cpu(clock);
212 if (sc->clkfreq == 0)
213 sc->clkfreq = DEFAULT_FREQ;
215 if (sc->clkfreq == 0) {
216 device_printf(dev, "No clock frequency specified\n");
220 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
221 device_printf(dev, "could not allocate resources\n");
225 /* Memory interface */
226 sc->bst = rman_get_bustag(sc->res[0]);
227 sc->bsh = rman_get_bushandle(sc->res[0]);
231 /* Setup IRQs handler */
232 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK,
233 riscv_tmr_intr, NULL, sc, &sc->ih);
235 device_printf(dev, "Unable to alloc int resource.\n");
239 riscv_tmr_timecount.tc_frequency = sc->clkfreq;
240 riscv_tmr_timecount.tc_priv = sc;
241 tc_init(&riscv_tmr_timecount);
243 sc->et.et_name = "RISC-V Eventtimer";
244 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
245 sc->et.et_quality = 1000;
247 sc->et.et_frequency = sc->clkfreq;
248 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
249 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
250 sc->et.et_start = riscv_tmr_start;
251 sc->et.et_stop = riscv_tmr_stop;
253 et_register(&sc->et);
258 static device_method_t riscv_tmr_fdt_methods[] = {
259 DEVMETHOD(device_probe, riscv_tmr_fdt_probe),
260 DEVMETHOD(device_attach, riscv_tmr_attach),
264 static driver_t riscv_tmr_fdt_driver = {
266 riscv_tmr_fdt_methods,
267 sizeof(struct riscv_tmr_softc),
270 static devclass_t riscv_tmr_fdt_devclass;
272 EARLY_DRIVER_MODULE(timer, simplebus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass,
273 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
274 EARLY_DRIVER_MODULE(timer, ofwbus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass,
275 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
280 int64_t counts, counts_per_usec;
281 uint64_t first, last;
284 * Check the timers are setup, if not just
285 * use a for loop for the meantime
287 if (riscv_tmr_sc == NULL) {
288 for (; usec > 0; usec--)
289 for (counts = 200; counts > 0; counts--)
291 * Prevent the compiler from optimizing
298 /* Get the number of times to count */
299 counts_per_usec = ((riscv_tmr_timecount.tc_frequency / 1000000) + 1);
302 * Clamp the timeout at a maximum value (about 32 seconds with
303 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
304 * near that length of time and if they are, they should be hung
307 if (usec >= (0x80000000U / counts_per_usec))
308 counts = (0x80000000U / counts_per_usec) - 1;
310 counts = usec * counts_per_usec;
312 first = get_counts(riscv_tmr_sc);
315 last = get_counts(riscv_tmr_sc);
316 counts -= (int64_t)(last - first);