sys/riscv/riscv/timer.c

   1 /*-
   2  * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * Portions of this software were developed by SRI International and the
   6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
   7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
   8  *
   9  * Portions of this software were developed by the University of Cambridge
  10  * Computer Laboratory as part of the CTSRD Project, with support from the
  11  * UK Higher Education Innovation Fund (HEIF).
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  * 1. Redistributions of source code must retain the above copyright
  17  *    notice, this list of conditions and the following disclaimer.
  18  * 2. Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 /*
  36  * RISC-V Timer
  37  */
  38
  39 #include "opt_platform.h"
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/bus.h>
  47 #include <sys/kernel.h>
  48 #include <sys/module.h>
  49 #include <sys/timeet.h>
  50 #include <sys/timetc.h>
  51 #include <sys/vdso.h>
  52 #include <sys/watchdog.h>
  53
  54 #include <machine/cpufunc.h>
  55 #include <machine/intr.h>
  56 #include <machine/md_var.h>
  57 #include <machine/sbi.h>
  58
  59 #include <dev/ofw/openfirm.h>
  60
  61 struct riscv_timer_softc {
  62         void                    *ih;
  63         uint32_t                clkfreq;
  64         struct eventtimer       et;
  65 };
  66 static struct riscv_timer_softc *riscv_timer_sc = NULL;
  67
  68 static timecounter_get_t riscv_timer_tc_get_timecount;
  69 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands;
  70
  71 static struct timecounter riscv_timer_timecount = {
  72         .tc_name           = "RISC-V Timecounter",
  73         .tc_get_timecount  = riscv_timer_tc_get_timecount,
  74         .tc_poll_pps       = NULL,
  75         .tc_counter_mask   = ~0u,
  76         .tc_frequency      = 0,
  77         .tc_quality        = 1000,
  78         .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands,
  79 };
  80
  81 static inline uint64_t
  82 get_timecount(void)
  83 {
  84
  85         return (rdtime());
  86 }
  87
  88 static inline void
  89 set_timecmp(uint64_t timecmp)
  90 {
  91
  92         if (has_sstc)
  93                 csr_write(stimecmp, timecmp);
  94         else
  95                 sbi_set_timer(timecmp);
  96 }
  97
  98 static u_int
  99 riscv_timer_tc_get_timecount(struct timecounter *tc __unused)
 100 {
 101
 102         return (get_timecount());
 103 }
 104
 105 static uint32_t
 106 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th,
 107     struct timecounter *tc)
 108 {
 109         vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME;
 110         bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
 111         return (1);
 112 }
 113
 114 static int
 115 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 116 {
 117         uint64_t counts;
 118
 119         if (first != 0) {
 120                 counts = ((uint32_t)et->et_frequency * first) >> 32;
 121                 set_timecmp(get_timecount() + counts);
 122                 csr_set(sie, SIE_STIE);
 123
 124                 return (0);
 125         }
 126
 127         return (EINVAL);
 128 }
 129
 130 static int
 131 riscv_timer_et_stop(struct eventtimer *et)
 132 {
 133
 134         /* Disable timer interrupts. */
 135         csr_clear(sie, SIE_STIE);
 136
 137         return (0);
 138 }
 139
 140 static int
 141 riscv_timer_intr(void *arg)
 142 {
 143         struct riscv_timer_softc *sc;
 144
 145         sc = (struct riscv_timer_softc *)arg;
 146
 147         csr_clear(sip, SIP_STIP);
 148
 149         if (sc->et.et_active)
 150                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 151
 152         return (FILTER_HANDLED);
 153 }
 154
 155 static int
 156 riscv_timer_get_timebase(device_t dev, uint32_t *freq)
 157 {
 158         phandle_t node;
 159         int len;
 160
 161         node = OF_finddevice("/cpus");
 162         if (node == -1) {
 163                 if (bootverbose)
 164                         device_printf(dev, "Can't find cpus node.\n");
 165                 return (ENXIO);
 166         }
 167
 168         len = OF_getproplen(node, "timebase-frequency");
 169         if (len != 4) {
 170                 if (bootverbose)
 171                         device_printf(dev,
 172                             "Can't find timebase-frequency property.\n");
 173                 return (ENXIO);
 174         }
 175
 176         OF_getencprop(node, "timebase-frequency", freq, len);
 177
 178         return (0);
 179 }
 180
 181 static int
 182 riscv_timer_probe(device_t dev)
 183 {
 184
 185         device_set_desc(dev, "RISC-V Timer");
 186
 187         return (BUS_PROBE_DEFAULT);
 188 }
 189
 190 static int
 191 riscv_timer_attach(device_t dev)
 192 {
 193         struct riscv_timer_softc *sc;
 194         int error;
 195
 196         sc = device_get_softc(dev);
 197         if (riscv_timer_sc != NULL)
 198                 return (ENXIO);
 199
 200         if (device_get_unit(dev) != 0)
 201                 return (ENXIO);
 202
 203         if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) {
 204                 device_printf(dev, "No clock frequency specified\n");
 205                 return (ENXIO);
 206         }
 207
 208         riscv_timer_sc = sc;
 209
 210         /* Setup IRQs handler */
 211         error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr,
 212             NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih);
 213         if (error) {
 214                 device_printf(dev, "Unable to alloc int resource.\n");
 215                 return (ENXIO);
 216         }
 217
 218         riscv_timer_timecount.tc_frequency = sc->clkfreq;
 219         riscv_timer_timecount.tc_priv = sc;
 220         tc_init(&riscv_timer_timecount);
 221
 222         sc->et.et_name = "RISC-V Eventtimer";
 223         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
 224         sc->et.et_quality = 1000;
 225
 226         sc->et.et_frequency = sc->clkfreq;
 227         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 228         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 229         sc->et.et_start = riscv_timer_et_start;
 230         sc->et.et_stop = riscv_timer_et_stop;
 231         sc->et.et_priv = sc;
 232         et_register(&sc->et);
 233
 234         set_cputicker(get_timecount, sc->clkfreq, false);
 235
 236         return (0);
 237 }
 238
 239 static device_method_t riscv_timer_methods[] = {
 240         DEVMETHOD(device_probe,         riscv_timer_probe),
 241         DEVMETHOD(device_attach,        riscv_timer_attach),
 242         { 0, 0 }
 243 };
 244
 245 static driver_t riscv_timer_driver = {
 246         "timer",
 247         riscv_timer_methods,
 248         sizeof(struct riscv_timer_softc),
 249 };
 250
 251 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, 0, 0,
 252     BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
 253
 254 void
 255 DELAY(int usec)
 256 {
 257         int64_t counts, counts_per_usec;
 258         uint64_t first, last;
 259
 260         /*
 261          * Check the timers are setup, if not just
 262          * use a for loop for the meantime
 263          */
 264         if (riscv_timer_sc == NULL) {
 265                 for (; usec > 0; usec--)
 266                         for (counts = 200; counts > 0; counts--)
 267                                 /*
 268                                  * Prevent the compiler from optimizing
 269                                  * out the loop
 270                                  */
 271                                 cpufunc_nullop();
 272                 return;
 273         }
 274         TSENTER();
 275
 276         /* Get the number of times to count */
 277         counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1);
 278
 279         /*
 280          * Clamp the timeout at a maximum value (about 32 seconds with
 281          * a 66MHz clock). *Nobody* should be delay()ing for anywhere
 282          * near that length of time and if they are, they should be hung
 283          * out to dry.
 284          */
 285         if (usec >= (0x80000000U / counts_per_usec))
 286                 counts = (0x80000000U / counts_per_usec) - 1;
 287         else
 288                 counts = usec * counts_per_usec;
 289
 290         first = get_timecount();
 291
 292         while (counts > 0) {
 293                 last = get_timecount();
 294                 counts -= (int64_t)(last - first);
 295                 first = last;
 296         }
 297         TSEXIT();
 298 }