2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include "opt_platform.h"
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/kernel.h>
48 #include <sys/module.h>
49 #include <sys/malloc.h>
51 #include <sys/timeet.h>
52 #include <sys/timetc.h>
53 #include <sys/watchdog.h>
57 #include <machine/bus.h>
58 #include <machine/cpu.h>
59 #include <machine/intr.h>
60 #include <machine/asm.h>
61 #include <machine/trap.h>
62 #include <machine/sbi.h>
64 #include <dev/fdt/fdt_common.h>
65 #include <dev/ofw/openfirm.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
69 #define DEFAULT_FREQ 1000000
71 #define TIMER_COUNTS 0x00
72 #define TIMER_MTIMECMP(cpu) (cpu * 8)
74 #define READ8(_sc, _reg) \
75 bus_space_read_8(_sc->bst, _sc->bsh, _reg)
76 #define WRITE8(_sc, _reg, _val) \
77 bus_space_write_8(_sc->bst, _sc->bsh, _reg, _val)
79 struct riscv_tmr_softc {
80 struct resource *res[3];
82 bus_space_handle_t bsh;
83 bus_space_tag_t bst_timecmp;
84 bus_space_handle_t bsh_timecmp;
90 static struct riscv_tmr_softc *riscv_tmr_sc = NULL;
92 static struct resource_spec timer_spec[] = {
93 { SYS_RES_MEMORY, 0, RF_ACTIVE },
94 { SYS_RES_MEMORY, 1, RF_ACTIVE },
95 { SYS_RES_IRQ, 0, RF_ACTIVE },
99 static timecounter_get_t riscv_tmr_get_timecount;
101 static struct timecounter riscv_tmr_timecount = {
102 .tc_name = "RISC-V Timecounter",
103 .tc_get_timecount = riscv_tmr_get_timecount,
105 .tc_counter_mask = ~0u,
111 get_counts(struct riscv_tmr_softc *sc)
115 counts = READ8(sc, TIMER_COUNTS);
121 riscv_tmr_get_timecount(struct timecounter *tc)
123 struct riscv_tmr_softc *sc;
127 return (get_counts(sc));
131 riscv_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
133 struct riscv_tmr_softc *sc;
137 sc = (struct riscv_tmr_softc *)et->et_priv;
140 counts = ((uint32_t)et->et_frequency * first) >> 32;
141 counts += READ8(sc, TIMER_COUNTS);
142 cpu = PCPU_GET(cpuid);
143 bus_space_write_8(sc->bst_timecmp, sc->bsh_timecmp,
144 TIMER_MTIMECMP(cpu), counts);
145 csr_set(sie, SIE_STIE);
146 sbi_set_timer(counts);
156 riscv_tmr_stop(struct eventtimer *et)
158 struct riscv_tmr_softc *sc;
160 sc = (struct riscv_tmr_softc *)et->et_priv;
168 riscv_tmr_intr(void *arg)
170 struct riscv_tmr_softc *sc;
172 sc = (struct riscv_tmr_softc *)arg;
174 csr_clear(sip, SIP_STIP);
176 if (sc->et.et_active)
177 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
179 return (FILTER_HANDLED);
183 riscv_tmr_fdt_probe(device_t dev)
186 if (!ofw_bus_status_okay(dev))
189 if (ofw_bus_is_compatible(dev, "riscv,timer")) {
190 device_set_desc(dev, "RISC-V Timer");
191 return (BUS_PROBE_DEFAULT);
198 riscv_tmr_attach(device_t dev)
200 struct riscv_tmr_softc *sc;
205 sc = device_get_softc(dev);
209 /* Get the base clock frequency */
210 node = ofw_bus_get_node(dev);
212 error = OF_getprop(node, "clock-frequency", &clock,
215 sc->clkfreq = fdt32_to_cpu(clock);
219 if (sc->clkfreq == 0)
220 sc->clkfreq = DEFAULT_FREQ;
222 if (sc->clkfreq == 0) {
223 device_printf(dev, "No clock frequency specified\n");
227 if (bus_alloc_resources(dev, timer_spec, sc->res)) {
228 device_printf(dev, "could not allocate resources\n");
232 /* Memory interface */
233 sc->bst = rman_get_bustag(sc->res[0]);
234 sc->bsh = rman_get_bushandle(sc->res[0]);
235 sc->bst_timecmp = rman_get_bustag(sc->res[1]);
236 sc->bsh_timecmp = rman_get_bushandle(sc->res[1]);
240 /* Setup IRQs handler */
241 error = bus_setup_intr(dev, sc->res[2], INTR_TYPE_CLK,
242 riscv_tmr_intr, NULL, sc, &sc->ih);
244 device_printf(dev, "Unable to alloc int resource.\n");
248 riscv_tmr_timecount.tc_frequency = sc->clkfreq;
249 riscv_tmr_timecount.tc_priv = sc;
250 tc_init(&riscv_tmr_timecount);
252 sc->et.et_name = "RISC-V Eventtimer";
253 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
254 sc->et.et_quality = 1000;
256 sc->et.et_frequency = sc->clkfreq;
257 sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
258 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
259 sc->et.et_start = riscv_tmr_start;
260 sc->et.et_stop = riscv_tmr_stop;
262 et_register(&sc->et);
267 static device_method_t riscv_tmr_fdt_methods[] = {
268 DEVMETHOD(device_probe, riscv_tmr_fdt_probe),
269 DEVMETHOD(device_attach, riscv_tmr_attach),
273 static driver_t riscv_tmr_fdt_driver = {
275 riscv_tmr_fdt_methods,
276 sizeof(struct riscv_tmr_softc),
279 static devclass_t riscv_tmr_fdt_devclass;
281 EARLY_DRIVER_MODULE(timer, simplebus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass,
282 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
283 EARLY_DRIVER_MODULE(timer, ofwbus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass,
284 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
289 int64_t counts, counts_per_usec;
290 uint64_t first, last;
293 * Check the timers are setup, if not just
294 * use a for loop for the meantime
296 if (riscv_tmr_sc == NULL) {
297 for (; usec > 0; usec--)
298 for (counts = 200; counts > 0; counts--)
300 * Prevent the compiler from optimizing
307 /* Get the number of times to count */
308 counts_per_usec = ((riscv_tmr_timecount.tc_frequency / 1000000) + 1);
311 * Clamp the timeout at a maximum value (about 32 seconds with
312 * a 66MHz clock). *Nobody* should be delay()ing for anywhere
313 * near that length of time and if they are, they should be hung
316 if (usec >= (0x80000000U / counts_per_usec))
317 counts = (0x80000000U / counts_per_usec) - 1;
319 counts = usec * counts_per_usec;
321 first = get_counts(riscv_tmr_sc);
324 last = get_counts(riscv_tmr_sc);
325 counts -= (int64_t)(last - first);