sys/riscv/riscv/timer.c

   1 /*-
   2  * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * Portions of this software were developed by SRI International and the
   6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
   7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
   8  *
   9  * Portions of this software were developed by the University of Cambridge
  10  * Computer Laboratory as part of the CTSRD Project, with support from the
  11  * UK Higher Education Innovation Fund (HEIF).
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  * 1. Redistributions of source code must retain the above copyright
  17  *    notice, this list of conditions and the following disclaimer.
  18  * 2. Redistributions in binary form must reproduce the above copyright
  19  *    notice, this list of conditions and the following disclaimer in the
  20  *    documentation and/or other materials provided with the distribution.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 /*
  36  * RISC-V Timer
  37  */
  38
  39 #include "opt_platform.h"
  40
  41 #include <sys/cdefs.h>
  42 __FBSDID("$FreeBSD$");
  43
  44 #include <sys/param.h>
  45 #include <sys/systm.h>
  46 #include <sys/bus.h>
  47 #include <sys/kernel.h>
  48 #include <sys/module.h>
  49 #include <sys/timeet.h>
  50 #include <sys/timetc.h>
  51 #include <sys/vdso.h>
  52 #include <sys/watchdog.h>
  53
  54 #include <machine/cpufunc.h>
  55 #include <machine/intr.h>
  56 #include <machine/sbi.h>
  57
  58 #include <dev/ofw/openfirm.h>
  59
  60 struct riscv_timer_softc {
  61         void                    *ih;
  62         uint32_t                clkfreq;
  63         struct eventtimer       et;
  64 };
  65 static struct riscv_timer_softc *riscv_timer_sc = NULL;
  66
  67 static timecounter_get_t riscv_timer_tc_get_timecount;
  68 static timecounter_fill_vdso_timehands_t riscv_timer_tc_fill_vdso_timehands;
  69
  70 static struct timecounter riscv_timer_timecount = {
  71         .tc_name           = "RISC-V Timecounter",
  72         .tc_get_timecount  = riscv_timer_tc_get_timecount,
  73         .tc_poll_pps       = NULL,
  74         .tc_counter_mask   = ~0u,
  75         .tc_frequency      = 0,
  76         .tc_quality        = 1000,
  77         .tc_fill_vdso_timehands = riscv_timer_tc_fill_vdso_timehands,
  78 };
  79
  80 static inline uint64_t
  81 get_cycles(void)
  82 {
  83
  84         return (rdtime());
  85 }
  86
  87 static long
  88 get_counts(struct riscv_timer_softc *sc)
  89 {
  90         uint64_t counts;
  91
  92         counts = get_cycles();
  93
  94         return (counts);
  95 }
  96
  97 static u_int
  98 riscv_timer_tc_get_timecount(struct timecounter *tc)
  99 {
 100         struct riscv_timer_softc *sc;
 101
 102         sc = tc->tc_priv;
 103
 104         return (get_counts(sc));
 105 }
 106
 107 static uint32_t
 108 riscv_timer_tc_fill_vdso_timehands(struct vdso_timehands *vdso_th,
 109     struct timecounter *tc)
 110 {
 111         vdso_th->th_algo = VDSO_TH_ALGO_RISCV_RDTIME;
 112         bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
 113         return (1);
 114 }
 115
 116 static int
 117 riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 118 {
 119         uint64_t counts;
 120
 121         if (first != 0) {
 122                 counts = ((uint32_t)et->et_frequency * first) >> 32;
 123                 sbi_set_timer(get_cycles() + counts);
 124                 csr_set(sie, SIE_STIE);
 125
 126                 return (0);
 127         }
 128
 129         return (EINVAL);
 130 }
 131
 132 static int
 133 riscv_timer_et_stop(struct eventtimer *et)
 134 {
 135
 136         /* Disable timer interrupts. */
 137         csr_clear(sie, SIE_STIE);
 138
 139         return (0);
 140 }
 141
 142 static int
 143 riscv_timer_intr(void *arg)
 144 {
 145         struct riscv_timer_softc *sc;
 146
 147         sc = (struct riscv_timer_softc *)arg;
 148
 149         csr_clear(sip, SIP_STIP);
 150
 151         if (sc->et.et_active)
 152                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
 153
 154         return (FILTER_HANDLED);
 155 }
 156
 157 static int
 158 riscv_timer_get_timebase(device_t dev, uint32_t *freq)
 159 {
 160         phandle_t node;
 161         int len;
 162
 163         node = OF_finddevice("/cpus");
 164         if (node == -1) {
 165                 if (bootverbose)
 166                         device_printf(dev, "Can't find cpus node.\n");
 167                 return (ENXIO);
 168         }
 169
 170         len = OF_getproplen(node, "timebase-frequency");
 171         if (len != 4) {
 172                 if (bootverbose)
 173                         device_printf(dev,
 174                             "Can't find timebase-frequency property.\n");
 175                 return (ENXIO);
 176         }
 177
 178         OF_getencprop(node, "timebase-frequency", freq, len);
 179
 180         return (0);
 181 }
 182
 183 static int
 184 riscv_timer_probe(device_t dev)
 185 {
 186
 187         device_set_desc(dev, "RISC-V Timer");
 188
 189         return (BUS_PROBE_DEFAULT);
 190 }
 191
 192 static int
 193 riscv_timer_attach(device_t dev)
 194 {
 195         struct riscv_timer_softc *sc;
 196         int error;
 197
 198         sc = device_get_softc(dev);
 199         if (riscv_timer_sc != NULL)
 200                 return (ENXIO);
 201
 202         if (device_get_unit(dev) != 0)
 203                 return (ENXIO);
 204
 205         if (riscv_timer_get_timebase(dev, &sc->clkfreq) != 0) {
 206                 device_printf(dev, "No clock frequency specified\n");
 207                 return (ENXIO);
 208         }
 209
 210         riscv_timer_sc = sc;
 211
 212         /* Setup IRQs handler */
 213         error = riscv_setup_intr(device_get_nameunit(dev), riscv_timer_intr,
 214             NULL, sc, IRQ_TIMER_SUPERVISOR, INTR_TYPE_CLK, &sc->ih);
 215         if (error) {
 216                 device_printf(dev, "Unable to alloc int resource.\n");
 217                 return (ENXIO);
 218         }
 219
 220         riscv_timer_timecount.tc_frequency = sc->clkfreq;
 221         riscv_timer_timecount.tc_priv = sc;
 222         tc_init(&riscv_timer_timecount);
 223
 224         sc->et.et_name = "RISC-V Eventtimer";
 225         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
 226         sc->et.et_quality = 1000;
 227
 228         sc->et.et_frequency = sc->clkfreq;
 229         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
 230         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
 231         sc->et.et_start = riscv_timer_et_start;
 232         sc->et.et_stop = riscv_timer_et_stop;
 233         sc->et.et_priv = sc;
 234         et_register(&sc->et);
 235
 236         set_cputicker(get_timecount, sc->clkfreq, false);
 237
 238         return (0);
 239 }
 240
 241 static device_method_t riscv_timer_methods[] = {
 242         DEVMETHOD(device_probe,         riscv_timer_probe),
 243         DEVMETHOD(device_attach,        riscv_timer_attach),
 244         { 0, 0 }
 245 };
 246
 247 static driver_t riscv_timer_driver = {
 248         "timer",
 249         riscv_timer_methods,
 250         sizeof(struct riscv_timer_softc),
 251 };
 252
 253 static devclass_t riscv_timer_devclass;
 254
 255 EARLY_DRIVER_MODULE(timer, nexus, riscv_timer_driver, riscv_timer_devclass,
 256     0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
 257
 258 void
 259 DELAY(int usec)
 260 {
 261         int64_t counts, counts_per_usec;
 262         uint64_t first, last;
 263
 264         /*
 265          * Check the timers are setup, if not just
 266          * use a for loop for the meantime
 267          */
 268         if (riscv_timer_sc == NULL) {
 269                 for (; usec > 0; usec--)
 270                         for (counts = 200; counts > 0; counts--)
 271                                 /*
 272                                  * Prevent the compiler from optimizing
 273                                  * out the loop
 274                                  */
 275                                 cpufunc_nullop();
 276                 return;
 277         }
 278         TSENTER();
 279
 280         /* Get the number of times to count */
 281         counts_per_usec = ((riscv_timer_timecount.tc_frequency / 1000000) + 1);
 282
 283         /*
 284          * Clamp the timeout at a maximum value (about 32 seconds with
 285          * a 66MHz clock). *Nobody* should be delay()ing for anywhere
 286          * near that length of time and if they are, they should be hung
 287          * out to dry.
 288          */
 289         if (usec >= (0x80000000U / counts_per_usec))
 290                 counts = (0x80000000U / counts_per_usec) - 1;
 291         else
 292                 counts = usec * counts_per_usec;
 293
 294         first = get_counts(riscv_timer_sc);
 295
 296         while (counts > 0) {
 297                 last = get_counts(riscv_timer_sc);
 298                 counts -= (int64_t)(last - first);
 299                 first = last;
 300         }
 301         TSEXIT();
 302 }