2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2019 Axiado Corporation
7 * This software was developed in part by Kristof Provost under contract for
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/cpu.h>
47 #include <dev/extres/clk/clk.h>
48 #include <dev/extres/clk/clk_fixed.h>
50 #include <dev/ofw/ofw_bus.h>
51 #include <dev/ofw/ofw_bus_subr.h>
52 #include <dev/ofw/openfirm.h>
54 #include <gnu/dts/include/dt-bindings/clock/sifive-fu540-prci.h>
56 static struct ofw_compat_data compat_data[] = {
57 { "sifive,aloeprci0", 1 },
58 { "sifive,ux00prci0", 1 },
59 { "sifive,fu540-c000-prci", 1 },
63 static struct resource_spec prci_spec[] = {
64 { SYS_RES_MEMORY, 0, RF_ACTIVE },
73 struct clkdom *clkdom;
76 bus_space_handle_t bsh;
79 struct prci_clk_pll_sc {
80 struct prci_softc *parent_sc;
84 #define PRCI_LOCK(sc) mtx_lock(&(sc)->mtx)
85 #define PRCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
86 #define PRCI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
87 #define PRCI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
89 #define PRCI_COREPLL_CFG0 0x4
90 #define PRCI_DDRPLL_CFG0 0xC
91 #define PRCI_GEMGXLPLL_CFG0 0x1C
93 #define PRCI_PLL_DIVR_MASK 0x3f
94 #define PRCI_PLL_DIVR_SHIFT 0
95 #define PRCI_PLL_DIVF_MASK 0x7fc0
96 #define PRCI_PLL_DIVF_SHIFT 6
97 #define PRCI_PLL_DIVQ_MASK 0x38000
98 #define PRCI_PLL_DIVQ_SHIFT 15
100 #define PRCI_READ(_sc, _reg) \
101 bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
103 struct prci_pll_def {
109 #define PLL(_id, _name, _base) \
117 struct prci_pll_def pll_clks[] = {
118 PLL(PRCI_CLK_COREPLL, "coreclk", PRCI_COREPLL_CFG0),
119 PLL(PRCI_CLK_DDRPLL, "ddrclk", PRCI_DDRPLL_CFG0),
120 PLL(PRCI_CLK_GEMGXLPLL, "gemgxclk", PRCI_GEMGXLPLL_CFG0),
123 /* Fixed divisor clock TLCLK. */
124 struct clk_fixed_def tlclk_def = {
125 .clkdef.id = PRCI_CLK_TLCLK,
126 .clkdef.name = "prci_tlclk",
127 .clkdef.parent_names = (const char *[]){"coreclk"},
128 .clkdef.parent_cnt = 1,
129 .clkdef.flags = CLK_NODE_STATIC_STRINGS,
135 prci_clk_pll_init(struct clknode *clk, device_t dev)
138 clknode_init_parent_idx(clk, 0);
144 prci_clk_pll_recalc(struct clknode *clk, uint64_t *freq)
146 struct prci_clk_pll_sc *sc;
147 struct clknode *parent_clk;
149 uint64_t refclk, divf, divq, divr;
152 KASSERT(freq != NULL, ("freq cannot be NULL"));
154 sc = clknode_get_softc(clk);
156 PRCI_LOCK(sc->parent_sc);
158 /* Get refclock frequency. */
159 parent_clk = clknode_get_parent(clk);
160 err = clknode_get_freq(parent_clk, &refclk);
162 device_printf(sc->parent_sc->dev,
163 "Failed to get refclk frequency\n");
164 PRCI_UNLOCK(sc->parent_sc);
168 /* Calculate the PLL output */
169 val = PRCI_READ(sc->parent_sc, sc->reg);
171 divf = (val & PRCI_PLL_DIVF_MASK) >> PRCI_PLL_DIVF_SHIFT;
172 divq = (val & PRCI_PLL_DIVQ_MASK) >> PRCI_PLL_DIVQ_SHIFT;
173 divr = (val & PRCI_PLL_DIVR_MASK) >> PRCI_PLL_DIVR_SHIFT;
175 *freq = refclk / (divr + 1) * (2 * (divf + 1)) / (1 << divq);
177 PRCI_UNLOCK(sc->parent_sc);
182 static clknode_method_t prci_clk_pll_clknode_methods[] = {
183 CLKNODEMETHOD(clknode_init, prci_clk_pll_init),
184 CLKNODEMETHOD(clknode_recalc_freq, prci_clk_pll_recalc),
188 DEFINE_CLASS_1(prci_clk_pll_clknode, prci_clk_pll_clknode_class,
189 prci_clk_pll_clknode_methods, sizeof(struct prci_clk_pll_sc),
193 prci_probe(device_t dev)
196 if (!ofw_bus_status_okay(dev))
199 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
202 device_set_desc(dev, "SiFive FU540 Power Reset Clocking Interrupt");
204 return (BUS_PROBE_DEFAULT);
208 prci_pll_register(struct prci_softc *parent_sc, struct clknode_init_def *clkdef,
212 struct prci_clk_pll_sc *sc;
214 clk = clknode_create(parent_sc->clkdom, &prci_clk_pll_clknode_class,
217 panic("Failed to create clknode");
219 sc = clknode_get_softc(clk);
220 sc->parent_sc = parent_sc;
223 clknode_register(parent_sc->clkdom, clk);
227 prci_attach(device_t dev)
229 struct clknode_init_def clkdef;
230 struct prci_softc *sc;
233 int i, ncells, error;
235 sc = device_get_softc(dev);
238 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
240 error = bus_alloc_resources(dev, prci_spec, &sc->res);
242 device_printf(dev, "Couldn't allocate resources\n");
245 sc->bst = rman_get_bustag(sc->res);
246 sc->bsh = rman_get_bushandle(sc->res);
248 node = ofw_bus_get_node(dev);
249 error = ofw_bus_parse_xref_list_get_length(node, "clocks",
250 "#clock-cells", &ncells);
251 if (error != 0 || ncells < 1) {
252 device_printf(dev, "couldn't find parent clock\n");
256 bzero(&clkdef, sizeof(clkdef));
257 clkdef.parent_names = mallocarray(ncells, sizeof(char *), M_OFWPROP,
259 for (i = 0; i < ncells; i++) {
260 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
262 device_printf(dev, "cannot get clock %d\n", error);
265 clkdef.parent_names[i] = clk_get_name(clk_parent);
267 device_printf(dev, "clk parent: %s\n",
268 clkdef.parent_names[i]);
269 clk_release(clk_parent);
271 clkdef.parent_cnt = ncells;
273 sc->clkdom = clkdom_create(dev);
274 if (sc->clkdom == NULL) {
275 device_printf(dev, "Couldn't create clock domain\n");
279 /* We can't free a clkdom, so from now on we cannot fail. */
280 for (i = 0; i < nitems(pll_clks); i++) {
281 clkdef.id = pll_clks[i].id;
282 clkdef.name = pll_clks[i].name;
283 prci_pll_register(sc, &clkdef, pll_clks[i].reg);
287 * Register the fixed clock "tlclk".
289 * If an older device tree is being used, tlclk may appear as its own
290 * entity in the device tree, under soc/tlclk. If this is the case it
291 * will be registered automatically by the fixed_clk driver, and the
292 * version we register here will be an unreferenced duplicate.
294 clknode_fixed_register(sc->clkdom, &tlclk_def);
296 error = clkdom_finit(sc->clkdom);
298 panic("Couldn't finalise clock domain");
303 free(clkdef.parent_names, M_OFWPROP);
306 bus_release_resources(dev, prci_spec, &sc->res);
307 mtx_destroy(&sc->mtx);
311 static device_method_t prci_methods[] = {
312 DEVMETHOD(device_probe, prci_probe),
313 DEVMETHOD(device_attach, prci_attach),
318 static driver_t prci_driver = {
321 sizeof(struct prci_softc)
324 static devclass_t prci_devclass;
326 EARLY_DRIVER_MODULE(fu540prci, simplebus, prci_driver, prci_devclass, 0, 0,