2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2019 Axiado Corporation
7 * This software was developed in part by Philip Paeps and Kristof Provost
8 * under contract for Axiado Corporation.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/cpu.h>
47 #include <dev/extres/clk/clk.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/ofw/openfirm.h>
53 #include <dev/spibus/spi.h>
54 #include <dev/spibus/spibusvar.h>
56 #include "spibus_if.h"
59 #define DBGPRINT(dev, fmt, args...) \
60 device_printf(dev, "%s: " fmt "\n", __func__, ## args)
62 #define DBGPRINT(dev, fmt, args...)
65 static struct resource_spec fuspi_spec[] = {
66 { SYS_RES_MEMORY, 0, RF_ACTIVE },
78 bus_space_handle_t bsh;
87 #define FUSPI_LOCK(sc) mtx_lock(&(sc)->mtx)
88 #define FUSPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
89 #define FUSPI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
90 #define FUSPI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
94 * From Sifive-Unleashed-FU540-C000-v1.0.pdf page 101.
96 #define FUSPI_REG_SCKDIV 0x00 /* Serial clock divisor */
97 #define FUSPI_REG_SCKMODE 0x04 /* Serial clock mode */
98 #define FUSPI_REG_CSID 0x10 /* Chip select ID */
99 #define FUSPI_REG_CSDEF 0x14 /* Chip select default */
100 #define FUSPI_REG_CSMODE 0x18 /* Chip select mode */
101 #define FUSPI_REG_DELAY0 0x28 /* Delay control 0 */
102 #define FUSPI_REG_DELAY1 0x2C /* Delay control 1 */
103 #define FUSPI_REG_FMT 0x40 /* Frame format */
104 #define FUSPI_REG_TXDATA 0x48 /* Tx FIFO data */
105 #define FUSPI_REG_RXDATA 0x4C /* Rx FIFO data */
106 #define FUSPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
107 #define FUSPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
108 #define FUSPI_REG_FCTRL 0x60 /* SPI flash interface control* */
109 #define FUSPI_REG_FFMT 0x64 /* SPI flash instruction format* */
110 #define FUSPI_REG_IE 0x70 /* SPI interrupt enable */
111 #define FUSPI_REG_IP 0x74 /* SPI interrupt pending */
113 #define FUSPI_SCKDIV_MASK 0xfff
115 #define FUSPI_CSDEF_ALL ((1 << sc->cs_max)-1)
117 #define FUSPI_CSMODE_AUTO 0x0U
118 #define FUSPI_CSMODE_HOLD 0x2U
119 #define FUSPI_CSMODE_OFF 0x3U
121 #define FUSPI_TXDATA_DATA_MASK 0xff
122 #define FUSPI_TXDATA_FULL (1 << 31)
124 #define FUSPI_RXDATA_DATA_MASK 0xff
125 #define FUSPI_RXDATA_EMPTY (1 << 31)
127 #define FUSPI_SCKMODE_PHA (1 << 0)
128 #define FUSPI_SCKMODE_POL (1 << 1)
130 #define FUSPI_FMT_PROTO_SINGLE 0x0U
131 #define FUSPI_FMT_PROTO_DUAL 0x1U
132 #define FUSPI_FMT_PROTO_QUAD 0x2U
133 #define FUSPI_FMT_PROTO_MASK 0x3U
134 #define FUSPI_FMT_ENDIAN (1 << 2)
135 #define FUSPI_FMT_DIR (1 << 3)
136 #define FUSPI_FMT_LEN(x) ((uint32_t)(x) << 16)
137 #define FUSPI_FMT_LEN_MASK (0xfU << 16)
139 #define FUSPI_FIFO_DEPTH 8
141 #define FUSPI_READ(_sc, _reg) \
142 bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
143 #define FUSPI_WRITE(_sc, _reg, _val) \
144 bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
147 fuspi_tx(struct fuspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
152 KASSERT(buf != NULL, ("TX buffer cannot be NULL"));
155 for (p = buf; p < end; p++) {
157 val = FUSPI_READ(sc, FUSPI_REG_TXDATA);
158 } while (val & FUSPI_TXDATA_FULL);
160 FUSPI_WRITE(sc, FUSPI_REG_TXDATA, val);
165 fuspi_rx(struct fuspi_softc *sc, uint8_t *buf, uint32_t bufsiz)
170 KASSERT(buf != NULL, ("RX buffer cannot be NULL"));
171 KASSERT(bufsiz <= FUSPI_FIFO_DEPTH,
172 ("Cannot receive more than %d bytes at a time\n",
176 for (p = buf; p < end; p++) {
178 val = FUSPI_READ(sc, FUSPI_REG_RXDATA);
179 } while (val & FUSPI_RXDATA_EMPTY);
180 *p = val & FUSPI_RXDATA_DATA_MASK;
185 fuspi_xfer_buf(struct fuspi_softc *sc, uint8_t *rxbuf, uint8_t *txbuf,
186 uint32_t txlen, uint32_t rxlen)
190 KASSERT(txlen == rxlen, ("TX and RX lengths must be equal"));
191 KASSERT(rxbuf != NULL, ("RX buffer cannot be NULL"));
192 KASSERT(txbuf != NULL, ("TX buffer cannot be NULL"));
195 bytes = (txlen > FUSPI_FIFO_DEPTH) ? FUSPI_FIFO_DEPTH : txlen;
196 fuspi_tx(sc, txbuf, bytes);
198 fuspi_rx(sc, rxbuf, bytes);
207 fuspi_setup(struct fuspi_softc *sc, uint32_t cs, uint32_t mode,
210 uint32_t csmode, fmt, sckdiv, sckmode;
212 FUSPI_ASSERT_LOCKED(sc);
215 * Fsck = Fin / 2 * (div + 1)
216 * -> div = Fin / (2 * Fsck) - 1
218 sckdiv = (howmany(sc->freq >> 1, freq) - 1) & FUSPI_SCKDIV_MASK;
219 FUSPI_WRITE(sc, FUSPI_REG_SCKDIV, sckdiv);
222 case SPIBUS_MODE_CPHA:
223 sckmode = FUSPI_SCKMODE_PHA;
225 case SPIBUS_MODE_CPOL:
226 sckmode = FUSPI_SCKMODE_POL;
228 case SPIBUS_MODE_CPOL_CPHA:
229 sckmode = FUSPI_SCKMODE_PHA | FUSPI_SCKMODE_POL;
232 FUSPI_WRITE(sc, FUSPI_REG_SCKMODE, sckmode);
234 csmode = FUSPI_CSMODE_HOLD;
235 if (cs & SPIBUS_CS_HIGH)
236 csmode = FUSPI_CSMODE_AUTO;
237 FUSPI_WRITE(sc, FUSPI_REG_CSMODE, csmode);
239 FUSPI_WRITE(sc, FUSPI_REG_CSID, cs & ~SPIBUS_CS_HIGH);
241 fmt = FUSPI_FMT_PROTO_SINGLE | FUSPI_FMT_LEN(8);
242 FUSPI_WRITE(sc, FUSPI_REG_FMT, fmt);
248 fuspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
250 struct fuspi_softc *sc;
251 uint32_t clock, cs, csdef, mode;
254 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
255 ("TX and RX command sizes must be equal"));
256 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
257 ("TX and RX data sizes must be equal"));
259 sc = device_get_softc(dev);
260 spibus_get_cs(child, &cs);
261 spibus_get_clock(child, &clock);
262 spibus_get_mode(child, &mode);
264 if (cs > sc->cs_max) {
265 device_printf(sc->dev, "Invalid chip select %u\n", cs);
270 device_busy(sc->dev);
272 err = fuspi_setup(sc, cs, mode, clock);
279 if (cmd->tx_cmd_sz > 0)
280 err = fuspi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd,
281 cmd->tx_cmd_sz, cmd->rx_cmd_sz);
282 if (cmd->tx_data_sz > 0 && err == 0)
283 err = fuspi_xfer_buf(sc, cmd->rx_data, cmd->tx_data,
284 cmd->tx_data_sz, cmd->rx_data_sz);
286 /* Deassert chip select. */
287 csdef = FUSPI_CSDEF_ALL & ~(1 << cs);
288 FUSPI_WRITE(sc, FUSPI_REG_CSDEF, csdef);
289 FUSPI_WRITE(sc, FUSPI_REG_CSDEF, FUSPI_CSDEF_ALL);
291 device_unbusy(sc->dev);
298 fuspi_attach(device_t dev)
300 struct fuspi_softc *sc;
303 sc = device_get_softc(dev);
306 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
308 error = bus_alloc_resources(dev, fuspi_spec, &sc->res);
310 device_printf(dev, "Couldn't allocate resources\n");
313 sc->bst = rman_get_bustag(sc->res);
314 sc->bsh = rman_get_bushandle(sc->res);
316 error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
318 device_printf(dev, "Couldn't allocate clock: %d\n", error);
321 error = clk_enable(sc->clk);
323 device_printf(dev, "Couldn't enable clock: %d\n", error);
327 error = clk_get_freq(sc->clk, &sc->freq);
329 device_printf(sc->dev, "Couldn't get frequency: %d\n", error);
334 * From Sifive-Unleashed-FU540-C000-v1.0.pdf page 103:
335 * csdef is cs_width bits wide and all ones on reset.
337 sc->cs_max = FUSPI_READ(sc, FUSPI_REG_CSDEF);
340 * We don't support the direct-mapped flash interface.
343 FUSPI_WRITE(sc, FUSPI_REG_FCTRL, 0x0);
345 /* Probe and attach the spibus when interrupts are available. */
346 sc->parent = device_add_child(dev, "spibus", -1);
347 config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
352 bus_release_resources(dev, fuspi_spec, &sc->res);
353 mtx_destroy(&sc->mtx);
358 fuspi_probe(device_t dev)
361 if (!ofw_bus_status_okay(dev))
364 if (!ofw_bus_is_compatible(dev, "sifive,spi0"))
367 device_set_desc(dev, "SiFive FU540 SPI controller");
369 return (BUS_PROBE_DEFAULT);
373 fuspi_get_node(device_t bus, device_t dev)
376 return (ofw_bus_get_node(bus));
379 static device_method_t fuspi_methods[] = {
380 DEVMETHOD(device_probe, fuspi_probe),
381 DEVMETHOD(device_attach, fuspi_attach),
383 DEVMETHOD(spibus_transfer, fuspi_transfer),
385 DEVMETHOD(ofw_bus_get_node, fuspi_get_node),
390 static driver_t fuspi_driver = {
393 sizeof(struct fuspi_softc)
396 static devclass_t fuspi_devclass;
398 DRIVER_MODULE(fu540spi, simplebus, fuspi_driver, fuspi_devclass, 0, 0);
399 DRIVER_MODULE(ofw_spibus, fu540spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0);
400 MODULE_DEPEND(fu540spi, ofw_spibus, 1, 1, 1);