2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright 2021 Jessica Clarke <jrtc27@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* SiFive FU740 DesignWare PCIe driver */
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
42 #include <machine/bus.h>
43 #include <machine/intr.h>
44 #include <machine/resource.h>
46 #include <dev/extres/clk/clk.h>
47 #include <dev/extres/hwreset/hwreset.h>
48 #include <dev/gpio/gpiobusvar.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/ofw/ofw_pci.h>
52 #include <dev/ofw/ofwpci.h>
53 #include <dev/pci/pcivar.h>
54 #include <dev/pci/pcireg.h>
55 #include <dev/pci/pcib_private.h>
56 #include <dev/pci/pci_dw.h>
59 #include "pci_dw_if.h"
62 #define FUDW_LANES_PER_PHY 4
64 #define FUDW_MGMT_PERST_N 0x0
65 #define FUDW_MGMT_LTSSM_EN 0x10
66 #define FUDW_MGMT_HOLD_PHY_RST 0x18
67 #define FUDW_MGMT_DEVICE_TYPE 0x708
68 #define FUDW_MGMT_DEVICE_TYPE_RC 0x4
69 #define FUDW_MGMT_PHY_CR_PARA_REG(_n, _r) \
70 (0x860 + (_n) * 0x40 + FUDW_MGMT_PHY_CR_PARA_##_r)
71 #define FUDW_MGMT_PHY_CR_PARA_ADDR 0x0
72 #define FUDW_MGMT_PHY_CR_PARA_READ_EN 0x10
73 #define FUDW_MGMT_PHY_CR_PARA_READ_DATA 0x18
74 #define FUDW_MGMT_PHY_CR_PARA_SEL 0x20
75 #define FUDW_MGMT_PHY_CR_PARA_WRITE_DATA 0x28
76 #define FUDW_MGMT_PHY_CR_PARA_WRITE_EN 0x30
77 #define FUDW_MGMT_PHY_CR_PARA_ACK 0x38
79 #define FUDW_MGMT_PHY_LANE(_n) (0x1008 + (_n) * 0x100)
80 #define FUDW_MGMT_PHY_LANE_CDR_TRACK_EN (1 << 0)
81 #define FUDW_MGMT_PHY_LANE_LOS_THRESH (1 << 5)
82 #define FUDW_MGMT_PHY_LANE_TERM_EN (1 << 9)
83 #define FUDW_MGMT_PHY_LANE_TERM_ACDC (1 << 10)
84 #define FUDW_MGMT_PHY_LANE_EN (1 << 11)
85 #define FUDW_MGMT_PHY_LANE_INIT \
86 (FUDW_MGMT_PHY_LANE_CDR_TRACK_EN | FUDW_MGMT_PHY_LANE_LOS_THRESH | \
87 FUDW_MGMT_PHY_LANE_TERM_EN | FUDW_MGMT_PHY_LANE_TERM_ACDC | \
88 FUDW_MGMT_PHY_LANE_EN)
90 #define FUDW_DBI_PORT_DBG1 0x72c
91 #define FUDW_DBI_PORT_DBG1_LINK_UP (1 << 4)
92 #define FUDW_DBI_PORT_DBG1_LINK_IN_TRAINING (1 << 29)
95 struct pci_dw_softc dw_sc;
97 struct resource *mgmt_res;
101 hwreset_t pcie_aux_rst;
104 #define FUDW_MGMT_READ(_sc, _o) bus_read_4((_sc)->mgmt_res, (_o))
105 #define FUDW_MGMT_WRITE(_sc, _o, _v) bus_write_4((_sc)->mgmt_res, (_o), (_v))
107 static struct ofw_compat_data compat_data[] = {
108 { "sifive,fu740-pcie", 1 },
112 /* Currently unused; included for completeness */
114 fupci_phy_read(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t *val)
119 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);
120 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_EN), 1);
124 ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
128 } while (--timeout > 0);
131 device_printf(sc->dev, "Timeout waiting for read ACK\n");
135 *val = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_DATA));
136 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, READ_EN), 0);
140 ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
144 } while (--timeout > 0);
147 device_printf(sc->dev, "Timeout waiting for read un-ACK\n");
155 fupci_phy_write(struct fupci_softc *sc, int phy, uint32_t reg, uint32_t val)
160 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ADDR), reg);
161 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_DATA), val);
162 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_EN), 1);
166 ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
170 } while (--timeout > 0);
173 device_printf(sc->dev, "Timeout waiting for write ACK\n");
177 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, WRITE_EN), 0);
181 ack = FUDW_MGMT_READ(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, ACK));
185 } while (--timeout > 0);
188 device_printf(sc->dev, "Timeout waiting for write un-ACK\n");
196 fupci_phy_init(struct fupci_softc *sc)
199 int error, phy, lane;
203 /* Assert core power-on reset (active low) */
204 error = gpio_pin_set_active(sc->porst_pin, false);
206 device_printf(dev, "Cannot assert power-on reset: %d\n",
212 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PERST_N, 0);
215 error = gpio_pin_set_active(sc->pwren_pin, true);
217 device_printf(dev, "Cannot enable power: %d\n", error);
221 /* Hold PERST for 100ms as per the PCIe spec */
224 /* Deassert PERST_N */
225 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PERST_N, 1);
227 /* Deassert core power-on reset (active low) */
228 error = gpio_pin_set_active(sc->porst_pin, true);
230 device_printf(dev, "Cannot deassert power-on reset: %d\n",
235 /* Enable the aux clock */
236 error = clk_enable(sc->pcie_aux_clk);
238 device_printf(dev, "Cannot enable aux clock: %d\n", error);
242 /* Hold LTSSM in reset whilst initialising the PHYs */
243 FUDW_MGMT_WRITE(sc, FUDW_MGMT_HOLD_PHY_RST, 1);
245 /* Deassert the aux reset */
246 error = hwreset_deassert(sc->pcie_aux_rst);
248 device_printf(dev, "Cannot deassert aux reset: %d\n", error);
252 /* Enable control register interface */
253 for (phy = 0; phy < FUDW_PHYS; ++phy)
254 FUDW_MGMT_WRITE(sc, FUDW_MGMT_PHY_CR_PARA_REG(phy, SEL), 1);
256 /* Wait for enable to take effect */
259 /* Initialise lane configuration */
260 for (phy = 0; phy < FUDW_PHYS; ++phy) {
261 for (lane = 0; lane < FUDW_LANES_PER_PHY; ++lane)
262 fupci_phy_write(sc, phy, FUDW_MGMT_PHY_LANE(lane),
263 FUDW_MGMT_PHY_LANE_INIT);
266 /* Disable the aux clock whilst taking the LTSSM out of reset */
267 error = clk_disable(sc->pcie_aux_clk);
269 device_printf(dev, "Cannot disable aux clock: %d\n", error);
273 /* Take LTSSM out of reset */
274 FUDW_MGMT_WRITE(sc, FUDW_MGMT_HOLD_PHY_RST, 0);
276 /* Enable the aux clock again */
277 error = clk_enable(sc->pcie_aux_clk);
279 device_printf(dev, "Cannot re-enable aux clock: %d\n", error);
283 /* Put the controller in Root Complex mode */
284 FUDW_MGMT_WRITE(sc, FUDW_MGMT_DEVICE_TYPE, FUDW_MGMT_DEVICE_TYPE_RC);
290 fupci_dbi_protect(struct fupci_softc *sc, bool protect)
294 reg = pci_dw_dbi_rd4(sc->dev, DW_MISC_CONTROL_1);
296 reg &= ~DBI_RO_WR_EN;
299 pci_dw_dbi_wr4(sc->dev, DW_MISC_CONTROL_1, reg);
303 fupci_init(struct fupci_softc *sc)
305 /* Enable 32-bit I/O window */
306 fupci_dbi_protect(sc, false);
307 pci_dw_dbi_wr2(sc->dev, PCIR_IOBASEL_1,
308 (PCIM_BRIO_32 << 8) | PCIM_BRIO_32);
309 fupci_dbi_protect(sc, true);
312 FUDW_MGMT_WRITE(sc, FUDW_MGMT_LTSSM_EN, 1);
318 fupci_probe(device_t dev)
320 if (!ofw_bus_status_okay(dev))
323 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
326 device_set_desc(dev, "SiFive FU740 PCIe Controller");
328 return (BUS_PROBE_DEFAULT);
332 fupci_attach(device_t dev)
334 struct fupci_softc *sc;
338 sc = device_get_softc(dev);
339 node = ofw_bus_get_node(dev);
343 error = ofw_bus_find_string_index(node, "reg-names", "dbi", &rid);
345 device_printf(dev, "Cannot get DBI memory: %d\n", error);
348 sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
350 if (sc->dw_sc.dbi_res == NULL) {
351 device_printf(dev, "Cannot allocate DBI memory\n");
357 error = ofw_bus_find_string_index(node, "reg-names", "mgmt", &rid);
359 device_printf(dev, "Cannot get management space memory: %d\n",
363 sc->mgmt_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
365 if (sc->mgmt_res == NULL) {
366 device_printf(dev, "Cannot allocate management space memory\n");
371 error = gpio_pin_get_by_ofw_property(dev, node, "reset-gpios",
373 /* Old U-Boot device tree uses perstn-gpios */
375 error = gpio_pin_get_by_ofw_property(dev, node, "perstn-gpios",
378 device_printf(dev, "Cannot get power-on reset GPIO: %d\n",
382 error = gpio_pin_setflags(sc->porst_pin, GPIO_PIN_OUTPUT);
384 device_printf(dev, "Cannot configure power-on reset GPIO: %d\n",
389 error = gpio_pin_get_by_ofw_property(dev, node, "pwren-gpios",
392 device_printf(dev, "Cannot get power enable GPIO: %d\n",
396 error = gpio_pin_setflags(sc->pwren_pin, GPIO_PIN_OUTPUT);
398 device_printf(dev, "Cannot configure power enable GPIO: %d\n",
403 error = clk_get_by_ofw_name(dev, node, "pcie_aux", &sc->pcie_aux_clk);
404 /* Old U-Boot device tree uses pcieaux */
406 error = clk_get_by_ofw_name(dev, node, "pcieaux",
409 device_printf(dev, "Cannot get aux clock: %d\n", error);
413 error = hwreset_get_by_ofw_idx(dev, node, 0, &sc->pcie_aux_rst);
415 device_printf(dev, "Cannot get aux reset: %d\n", error);
419 error = fupci_phy_init(sc);
423 error = pci_dw_init(dev);
427 error = fupci_init(sc);
431 return (bus_generic_attach(dev));
439 fupci_get_link(device_t dev, bool *status)
443 reg = pci_dw_dbi_rd4(dev, FUDW_DBI_PORT_DBG1);
444 *status = (reg & FUDW_DBI_PORT_DBG1_LINK_UP) != 0 &&
445 (reg & FUDW_DBI_PORT_DBG1_LINK_IN_TRAINING) == 0;
450 static device_method_t fupci_methods[] = {
451 /* Device interface */
452 DEVMETHOD(device_probe, fupci_probe),
453 DEVMETHOD(device_attach, fupci_attach),
455 /* PCI DW interface */
456 DEVMETHOD(pci_dw_get_link, fupci_get_link),
461 DEFINE_CLASS_1(pcib, fupci_driver, fupci_methods,
462 sizeof(struct fupci_softc), pci_dw_driver);
463 static devclass_t fupci_devclass;
464 DRIVER_MODULE(fu740_pci_dw, simplebus, fupci_driver, fupci_devclass,