2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2021 Jessica Clarke <jrtc27@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 /* TODO: Provide interrupt controller interface */
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <dev/gpio/gpiobusvar.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
48 #include <machine/bus.h>
50 /* Registers are 32-bit so can only fit 32 pins */
51 #define SFGPIO_MAX_PINS 32
53 #define SFGPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
55 #define SFGPIO_INPUT_VAL 0x0
56 #define SFGPIO_INPUT_EN 0x4
57 #define SFGPIO_OUTPUT_EN 0x8
58 #define SFGPIO_OUTPUT_VAL 0xc
59 #define SFGPIO_RISE_IE 0x18
60 #define SFGPIO_RISE_IP 0x1c
61 #define SFGPIO_FALL_IE 0x20
62 #define SFGPIO_FALL_IP 0x24
63 #define SFGPIO_HIGH_IE 0x28
64 #define SFGPIO_HIGH_IP 0x2c
65 #define SFGPIO_LOW_IE 0x30
66 #define SFGPIO_LOW_IP 0x34
72 struct resource *mem_res;
74 struct resource *irq_res;
77 struct gpio_pin gpio_pins[SFGPIO_MAX_PINS];
80 #define SFGPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
81 #define SFGPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
83 #define SFGPIO_READ(_sc, _off) \
84 bus_read_4((_sc)->mem_res, (_off))
85 #define SFGPIO_WRITE(_sc, _off, _val) \
86 bus_write_4((_sc)->mem_res, (_off), (_val))
88 static struct ofw_compat_data compat_data[] = {
89 { "sifive,gpio0", 1 },
94 sfgpio_probe(device_t dev)
96 if (!ofw_bus_status_okay(dev))
99 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
102 device_set_desc(dev, "SiFive GPIO Controller");
104 return (BUS_PROBE_DEFAULT);
108 sfgpio_attach(device_t dev)
110 struct sfgpio_softc *sc;
114 uint32_t input_en, output_en;
116 sc = device_get_softc(dev);
119 node = ofw_bus_get_node(dev);
121 mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
124 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
125 &sc->mem_rid, RF_ACTIVE);
126 if (sc->mem_res == NULL) {
127 device_printf(dev, "Cannot allocate memory resource\n");
132 if (OF_getencprop(node, "ngpios", &npins, sizeof(npins)) <= 0) {
133 /* Optional; defaults to 16 */
135 } else if (npins > SFGPIO_MAX_PINS) {
136 device_printf(dev, "Too many pins: %d\n", npins);
143 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
145 if (sc->irq_res == NULL) {
146 device_printf(dev, "Cannot allocate IRQ resource\n");
151 input_en = SFGPIO_READ(sc, SFGPIO_INPUT_EN);
152 output_en = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN);
153 for (i = 0; i < sc->npins; ++i) {
154 sc->gpio_pins[i].gp_pin = i;
155 sc->gpio_pins[i].gp_caps = SFGPIO_DEFAULT_CAPS;
156 sc->gpio_pins[i].gp_flags =
157 ((input_en & (1u << i)) ? GPIO_PIN_INPUT : 0) |
158 ((output_en & (1u << i)) ? GPIO_PIN_OUTPUT : 0);
159 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "GPIO%d", i);
160 sc->gpio_pins[i].gp_name[GPIOMAXNAME - 1] = '\0';
163 sc->busdev = gpiobus_attach_bus(dev);
164 if (sc->busdev == NULL) {
165 device_printf(dev, "Cannot attach gpiobus\n");
173 if (sc->busdev != NULL)
174 gpiobus_detach_bus(dev);
175 if (sc->irq_res != NULL)
176 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
178 if (sc->mem_res != NULL)
179 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
181 mtx_destroy(&sc->mtx);
186 sfgpio_get_bus(device_t dev)
188 struct sfgpio_softc *sc;
190 sc = device_get_softc(dev);
196 sfgpio_pin_max(device_t dev, int *maxpin)
198 struct sfgpio_softc *sc;
200 sc = device_get_softc(dev);
202 *maxpin = sc->npins - 1;
208 sfgpio_pin_set(device_t dev, uint32_t pin, unsigned int val)
210 struct sfgpio_softc *sc;
213 sc = device_get_softc(dev);
215 if (pin >= sc->npins)
219 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
224 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg);
231 sfgpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
233 struct sfgpio_softc *sc;
236 sc = device_get_softc(dev);
238 if (pin >= sc->npins)
242 if (sc->gpio_pins[pin].gp_flags & GPIO_PIN_OUTPUT)
243 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
245 reg = SFGPIO_READ(sc, SFGPIO_INPUT_VAL);
246 *val = (reg & (1u << pin)) ? 1 : 0;
253 sfgpio_pin_toggle(device_t dev, uint32_t pin)
255 struct sfgpio_softc *sc;
258 sc = device_get_softc(dev);
260 if (pin >= sc->npins)
264 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
266 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg);
273 sfgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
275 struct sfgpio_softc *sc;
277 sc = device_get_softc(dev);
279 if (pin >= sc->npins)
283 *caps = sc->gpio_pins[pin].gp_caps;
290 sfgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
292 struct sfgpio_softc *sc;
294 sc = device_get_softc(dev);
296 if (pin >= sc->npins)
300 *flags = sc->gpio_pins[pin].gp_flags;
307 sfgpio_pin_getname(device_t dev, uint32_t pin, char *name)
309 struct sfgpio_softc *sc;
311 sc = device_get_softc(dev);
313 if (pin >= sc->npins)
317 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
324 sfgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
326 struct sfgpio_softc *sc;
329 sc = device_get_softc(dev);
331 if (pin >= sc->npins)
336 reg = SFGPIO_READ(sc, SFGPIO_INPUT_EN);
337 if (flags & GPIO_PIN_INPUT) {
339 sc->gpio_pins[pin].gp_flags |= GPIO_PIN_INPUT;
342 sc->gpio_pins[pin].gp_flags &= ~GPIO_PIN_INPUT;
344 SFGPIO_WRITE(sc, SFGPIO_INPUT_EN, reg);
346 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN);
347 if (flags & GPIO_PIN_OUTPUT) {
349 sc->gpio_pins[pin].gp_flags |= GPIO_PIN_OUTPUT;
352 sc->gpio_pins[pin].gp_flags &= ~GPIO_PIN_OUTPUT;
354 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_EN, reg);
362 sfgpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
363 uint32_t change_pins, uint32_t *orig_pins)
365 struct sfgpio_softc *sc;
371 sc = device_get_softc(dev);
375 reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
377 if (orig_pins != NULL)
378 /* Only input_val is implicitly masked by input_en */
379 *orig_pins = SFGPIO_READ(sc, SFGPIO_INPUT_VAL) |
380 (reg & SFGPIO_READ(sc, SFGPIO_OUTPUT_EN));
382 if ((clear_pins | change_pins) != 0)
383 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL,
384 (reg & ~clear_pins) ^ change_pins);
392 sfgpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
395 struct sfgpio_softc *sc;
399 sc = device_get_softc(dev);
401 if (first_pin != 0 || num_pins > sc->npins)
406 ireg = SFGPIO_READ(sc, SFGPIO_INPUT_EN);
407 oreg = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN);
408 for (i = 0; i < num_pins; ++i) {
409 if (pin_flags[i] & GPIO_PIN_INPUT) {
412 sc->gpio_pins[i].gp_flags |= GPIO_PIN_INPUT;
413 sc->gpio_pins[i].gp_flags &= ~GPIO_PIN_OUTPUT;
414 } else if (pin_flags[i] & GPIO_PIN_OUTPUT) {
417 sc->gpio_pins[i].gp_flags &= ~GPIO_PIN_INPUT;
418 sc->gpio_pins[i].gp_flags |= GPIO_PIN_OUTPUT;
421 SFGPIO_WRITE(sc, SFGPIO_INPUT_EN, ireg);
422 SFGPIO_WRITE(sc, SFGPIO_OUTPUT_EN, oreg);
430 sfgpio_get_node(device_t bus, device_t dev)
432 return (ofw_bus_get_node(bus));
435 static device_method_t sfgpio_methods[] = {
436 /* Device interface */
437 DEVMETHOD(device_probe, sfgpio_probe),
438 DEVMETHOD(device_attach, sfgpio_attach),
441 DEVMETHOD(gpio_get_bus, sfgpio_get_bus),
442 DEVMETHOD(gpio_pin_max, sfgpio_pin_max),
443 DEVMETHOD(gpio_pin_set, sfgpio_pin_set),
444 DEVMETHOD(gpio_pin_get, sfgpio_pin_get),
445 DEVMETHOD(gpio_pin_toggle, sfgpio_pin_toggle),
446 DEVMETHOD(gpio_pin_getcaps, sfgpio_pin_getcaps),
447 DEVMETHOD(gpio_pin_getflags, sfgpio_pin_getflags),
448 DEVMETHOD(gpio_pin_getname, sfgpio_pin_getname),
449 DEVMETHOD(gpio_pin_setflags, sfgpio_pin_setflags),
450 DEVMETHOD(gpio_pin_access_32, sfgpio_pin_access_32),
451 DEVMETHOD(gpio_pin_config_32, sfgpio_pin_config_32),
453 /* ofw_bus interface */
454 DEVMETHOD(ofw_bus_get_node, sfgpio_get_node),
459 static devclass_t sfgpio_devclass;
460 DEFINE_CLASS_0(gpio, sfgpio_driver, sfgpio_methods,
461 sizeof(struct sfgpio_softc));
462 EARLY_DRIVER_MODULE(gpio, simplebus, sfgpio_driver, sfgpio_devclass, 0, 0,
463 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
464 MODULE_DEPEND(sfgpio, gpiobus, 1, 1, 1);