2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2019 Axiado Corporation
7 * This software was developed in part by Kristof Provost under contract for
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/kernel.h>
40 #include <sys/module.h>
41 #include <sys/mutex.h>
44 #include <machine/bus.h>
45 #include <machine/cpu.h>
47 #include <dev/extres/clk/clk.h>
49 #include <dev/ofw/ofw_bus.h>
50 #include <dev/ofw/ofw_bus_subr.h>
51 #include <dev/ofw/openfirm.h>
53 #include <dev/uart/uart.h>
54 #include <dev/uart/uart_bus.h>
55 #include <dev/uart/uart_cpu.h>
56 #include <dev/uart/uart_cpu_fdt.h>
60 #define SFUART_TXDATA 0x00
61 #define SFUART_TXDATA_FULL (1 << 31)
62 #define SFUART_RXDATA 0x04
63 #define SFUART_RXDATA_EMPTY (1 << 31)
64 #define SFUART_TXCTRL 0x08
65 #define SFUART_TXCTRL_ENABLE 0x01
66 #define SFUART_TXCTRL_NSTOP 0x02
67 #define SFUART_TXCTRL_TXCNT 0x70000
68 #define SFUART_TXCTRL_TXCNT_SHIFT 16
69 #define SFUART_RXCTRL 0x0c
70 #define SFUART_RXCTRL_ENABLE 0x01
71 #define SFUART_RXCTRL_RXCNT 0x70000
72 #define SFUART_RXCTRL_RXCNT_SHIFT 16
73 #define SFUART_IRQ_ENABLE 0x10
74 #define SFUART_IRQ_ENABLE_TXWM 0x01
75 #define SFUART_IRQ_ENABLE_RXWM 0x02
76 #define SFUART_IRQ_PENDING 0x14
77 #define SFUART_IRQ_PENDING_TXWM 0x01
78 #define SFUART_IRQ_PENDING_RXQM 0x02
79 #define SFUART_DIV 0x18
80 #define SFUART_REGS_SIZE 0x1c
82 #define SFUART_RX_FIFO_DEPTH 8
83 #define SFUART_TX_FIFO_DEPTH 8
86 struct uart_softc uart_softc;
91 sfuart_probe(struct uart_bas *bas)
100 sfuart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
105 uart_setreg(bas, SFUART_IRQ_ENABLE, 0);
107 /* Enable RX and configure the watermark so that we get an interrupt
108 * when a single character arrives (if interrupts are enabled). */
109 reg = SFUART_RXCTRL_ENABLE;
110 reg |= (0 << SFUART_RXCTRL_RXCNT_SHIFT);
111 uart_setreg(bas, SFUART_RXCTRL, reg);
113 /* Enable TX and configure the watermark so that we get an interrupt
114 * when there's room for one more character in the TX fifo (if
115 * interrupts are enabled). */
116 reg = SFUART_TXCTRL_ENABLE;
117 reg |= (1 << SFUART_TXCTRL_TXCNT_SHIFT);
119 reg |= SFUART_TXCTRL_NSTOP;
120 uart_setreg(bas, SFUART_TXCTRL, reg);
122 /* Don't touch DIV. Assume that's set correctly until we can
127 sfuart_putc(struct uart_bas *bas, int c)
130 while ((uart_getreg(bas, SFUART_TXDATA) & SFUART_TXDATA_FULL)
134 uart_setreg(bas, SFUART_TXDATA, c);
138 sfuart_rxready(struct uart_bas *bas)
141 return ((uart_getreg(bas, SFUART_RXDATA) &
142 SFUART_RXDATA_EMPTY) == 0);
146 sfuart_getc(struct uart_bas *bas, struct mtx *hwmtx)
152 while (((c = uart_getreg(bas, SFUART_RXDATA)) &
153 SFUART_RXDATA_EMPTY) != 0) {
165 sfuart_bus_probe(struct uart_softc *sc)
169 error = sfuart_probe(&sc->sc_bas);
173 sc->sc_rxfifosz = SFUART_RX_FIFO_DEPTH;
174 sc->sc_txfifosz = SFUART_TX_FIFO_DEPTH;
178 device_set_desc(sc->sc_dev, "SiFive UART");
184 sfuart_bus_attach(struct uart_softc *sc)
186 struct uart_bas *bas;
187 struct sfuart_softc *sfsc;
192 sfsc = (struct sfuart_softc *)sc;
195 error = clk_get_by_ofw_index(sc->sc_dev, 0, 0, &sfsc->clk);
197 device_printf(sc->sc_dev, "couldn't allocate clock\n");
201 error = clk_enable(sfsc->clk);
203 device_printf(sc->sc_dev, "couldn't enable clock\n");
207 error = clk_get_freq(sfsc->clk, &freq);
208 if (error || freq == 0) {
209 clk_disable(sfsc->clk);
210 device_printf(sc->sc_dev, "couldn't get clock frequency\n");
217 reg = SFUART_RXCTRL_ENABLE;
218 reg |= (0 << SFUART_RXCTRL_RXCNT_SHIFT);
219 uart_setreg(bas, SFUART_RXCTRL, reg);
221 reg = SFUART_TXCTRL_ENABLE;
222 reg |= (1 << SFUART_TXCTRL_TXCNT_SHIFT);
223 uart_setreg(bas, SFUART_TXCTRL, reg);
225 /* Enable RX interrupt */
226 uart_setreg(bas, SFUART_IRQ_ENABLE, SFUART_IRQ_ENABLE_RXWM);
232 sfuart_bus_detach(struct uart_softc *sc)
234 struct sfuart_softc *sfsc;
235 struct uart_bas *bas;
237 sfsc = (struct sfuart_softc *)sc;
241 uart_setreg(bas, SFUART_RXCTRL, 0);
242 uart_setreg(bas, SFUART_TXCTRL, 0);
244 /* Disable interrupts */
245 uart_setreg(bas, SFUART_IRQ_ENABLE, 0);
247 clk_disable(sfsc->clk);
253 sfuart_bus_flush(struct uart_softc *sc, int what)
255 struct uart_bas *bas;
259 uart_lock(sc->sc_hwmtx);
261 if (what & UART_FLUSH_TRANSMITTER) {
263 reg = uart_getreg(bas, SFUART_TXDATA);
264 } while ((reg & SFUART_TXDATA_FULL) != 0);
267 if (what & UART_FLUSH_RECEIVER) {
269 reg = uart_getreg(bas, SFUART_RXDATA);
270 } while ((reg & SFUART_RXDATA_EMPTY) == 0);
272 uart_unlock(sc->sc_hwmtx);
277 #define SIGCHG(c, i, s, d) \
280 i |= ((i) & (s)) ? (s) : (s) | (d); \
282 i = ((i) & (s)) ? (i) & ~(s) | (d) : (i); \
286 sfuart_bus_getsig(struct uart_softc *sc)
288 uint32_t new, old, sig;
293 SIGCHG(1, sig, SER_DSR, SER_DDSR);
294 SIGCHG(1, sig, SER_DCD, SER_DDCD);
295 SIGCHG(1, sig, SER_CTS, SER_DCTS);
296 new = sig & ~SER_MASK_DELTA;
297 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
303 sfuart_bus_setsig(struct uart_softc *sc, int sig)
310 if (sig & SER_DDTR) {
311 SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
313 if (sig & SER_DRTS) {
314 SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
316 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
322 sfuart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
324 struct uart_bas *bas;
330 uart_lock(sc->sc_hwmtx);
333 case UART_IOCTL_BAUD:
334 reg = uart_getreg(bas, SFUART_DIV);
336 /* Possible if the divisor hasn't been set up yet. */
340 *(int*)data = bas->rclk / (reg + 1);
348 uart_unlock(sc->sc_hwmtx);
354 sfuart_bus_ipend(struct uart_softc *sc)
356 struct uart_bas *bas;
361 uart_lock(sc->sc_hwmtx);
364 reg = uart_getreg(bas, SFUART_IRQ_PENDING);
365 ie = uart_getreg(bas, SFUART_IRQ_ENABLE);
367 if ((reg & SFUART_IRQ_PENDING_TXWM) != 0 &&
368 (ie & SFUART_IRQ_ENABLE_TXWM) != 0) {
369 ipend |= SER_INT_TXIDLE;
371 /* Disable TX interrupt */
372 ie &= ~(SFUART_IRQ_ENABLE_TXWM);
373 uart_setreg(bas, SFUART_IRQ_ENABLE, ie);
376 if ((reg & SFUART_IRQ_PENDING_RXQM) != 0)
377 ipend |= SER_INT_RXREADY;
379 uart_unlock(sc->sc_hwmtx);
385 sfuart_bus_param(struct uart_softc *sc, int baudrate, int databits,
386 int stopbits, int parity)
388 struct uart_bas *bas;
396 if (parity != UART_PARITY_NONE)
399 uart_lock(sc->sc_hwmtx);
401 reg = uart_getreg(bas, SFUART_TXCTRL);
403 reg |= SFUART_TXCTRL_NSTOP;
404 } else if (stopbits == 1) {
405 reg &= ~SFUART_TXCTRL_NSTOP;
407 uart_unlock(sc->sc_hwmtx);
411 if (baudrate > 0 && bas->rclk != 0) {
412 reg = (bas->rclk / baudrate) - 1;
413 uart_setreg(bas, SFUART_DIV, reg);
416 uart_unlock(sc->sc_hwmtx);
421 sfuart_bus_receive(struct uart_softc *sc)
423 struct uart_bas *bas;
427 uart_lock(sc->sc_hwmtx);
429 reg = uart_getreg(bas, SFUART_RXDATA);
430 while ((reg & SFUART_RXDATA_EMPTY) == 0) {
431 if (uart_rx_full(sc)) {
432 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
436 uart_rx_put(sc, reg & 0xff);
438 reg = uart_getreg(bas, SFUART_RXDATA);
441 uart_unlock(sc->sc_hwmtx);
447 sfuart_bus_transmit(struct uart_softc *sc)
449 struct uart_bas *bas;
454 uart_lock(sc->sc_hwmtx);
456 reg = uart_getreg(bas, SFUART_IRQ_ENABLE);
457 reg |= SFUART_IRQ_ENABLE_TXWM;
458 uart_setreg(bas, SFUART_IRQ_ENABLE, reg);
460 for (i = 0; i < sc->sc_txdatasz; i++)
461 sfuart_putc(bas, sc->sc_txbuf[i]);
465 uart_unlock(sc->sc_hwmtx);
471 sfuart_bus_grab(struct uart_softc *sc)
473 struct uart_bas *bas;
477 uart_lock(sc->sc_hwmtx);
479 reg = uart_getreg(bas, SFUART_IRQ_ENABLE);
480 reg &= ~(SFUART_IRQ_ENABLE_TXWM | SFUART_IRQ_PENDING_RXQM);
481 uart_setreg(bas, SFUART_IRQ_ENABLE, reg);
483 uart_unlock(sc->sc_hwmtx);
487 sfuart_bus_ungrab(struct uart_softc *sc)
489 struct uart_bas *bas;
493 uart_lock(sc->sc_hwmtx);
495 reg = uart_getreg(bas, SFUART_IRQ_ENABLE);
496 reg |= SFUART_IRQ_ENABLE_TXWM | SFUART_IRQ_PENDING_RXQM;
497 uart_setreg(bas, SFUART_IRQ_ENABLE, reg);
499 uart_unlock(sc->sc_hwmtx);
502 static kobj_method_t sfuart_methods[] = {
503 KOBJMETHOD(uart_probe, sfuart_bus_probe),
504 KOBJMETHOD(uart_attach, sfuart_bus_attach),
505 KOBJMETHOD(uart_detach, sfuart_bus_detach),
506 KOBJMETHOD(uart_flush, sfuart_bus_flush),
507 KOBJMETHOD(uart_getsig, sfuart_bus_getsig),
508 KOBJMETHOD(uart_setsig, sfuart_bus_setsig),
509 KOBJMETHOD(uart_ioctl, sfuart_bus_ioctl),
510 KOBJMETHOD(uart_ipend, sfuart_bus_ipend),
511 KOBJMETHOD(uart_param, sfuart_bus_param),
512 KOBJMETHOD(uart_receive, sfuart_bus_receive),
513 KOBJMETHOD(uart_transmit, sfuart_bus_transmit),
514 KOBJMETHOD(uart_grab, sfuart_bus_grab),
515 KOBJMETHOD(uart_ungrab, sfuart_bus_ungrab),
519 static struct uart_ops sfuart_ops = {
520 .probe = sfuart_probe,
524 .rxready = sfuart_rxready,
528 struct uart_class sfuart_class = {
531 sizeof(struct sfuart_softc),
532 .uc_ops = &sfuart_ops,
533 .uc_range = SFUART_REGS_SIZE,
538 static struct ofw_compat_data compat_data[] = {
539 { "sifive,uart0", (uintptr_t)&sfuart_class },
540 { NULL, (uintptr_t)NULL }
543 UART_FDT_CLASS_AND_DEVICE(compat_data);