2 /* $OpenBSD: ebusreg.h,v 1.4 2001/10/01 18:08:04 jason Exp $ */
3 /* $NetBSD: ebusreg.h,v 1.8 2008/05/29 14:51:27 mrg Exp $ */
6 * Copyright (c) 1999 Matthew R. Green
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * The `ebus' bus is designed to plug traditional PC-ISA devices into
36 * an SPARC system with as few costs as possible, without sacrificing
37 * to performance. Typically, it is implemented in the PCIO IC from
38 * SME, which also implements a `hme-compatible' PCI network device
39 * (`network'). The ebus has 4 DMA channels, similar to the DMA seen
40 * in the ESP SCSI DMA.
42 * Typical UltraSPARC systems have a NatSemi SuperIO IC to provide
43 * serial ports for the keyboard and mouse (`se'), floppy disk
44 * controller (`fdthree'), parallel port controller (`bpp') connected
45 * to the ebus, and a PCI-IDE controller (connected directly to the
46 * PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual
47 * channel serial controller (`su' providing ttya and ttyb), an MK48T59
48 * EEPROM/clock controller (also where the idprom, including the
49 * ethernet address, is located), the audio system (`SUNW,CS4231', same
50 * as other UltraSPARC and some SPARC systems), and other various
51 * internal devices found on traditional SPARC systems such as the
52 * `power', `flashprom', etc., devices.
54 * The ebus uses an interrupt mapping scheme similar to PCI, though
55 * the actual structures are different.
58 /* EBUS dma registers */
59 #define EBDMA_DCSR 0x0 /* control/status */
60 #define EBDMA_DADDR 0x4 /* DMA address */
61 #define EBDMA_DCNT 0x8 /* DMA count */
63 /* EBUS DMA control/status (EBDMA_DCSR) */
64 #define EBDCSR_INT 0x00000001 /* interrupt pending */
65 #define EBDCSR_ERR 0x00000002 /* error pending */
66 #define EBDCSR_DRAIN 0x00000004 /* drain */
67 #define EBDCSR_INTEN 0x00000010 /* interrupt enable */
68 #define EBDCSR_RESET 0x00000080 /* reset */
69 #define EBDCSR_WRITE 0x00000100 /* write */
70 #define EBDCSR_DMAEN 0x00000200 /* dma enable */
71 #define EBDCSR_CYC 0x00000400 /* cyc pending */
72 #define EBDCSR_DIAGRD 0x00000800 /* diagnostic read done */
73 #define EBDCSR_DIAGWR 0x00001000 /* diagnostic write done */
74 #define EBDCSR_CNTEN 0x00002000 /* count enable */
75 #define EBDCSR_TC 0x00004000 /* terminal count */
76 #define EBDCSR_CSRDRNDIS 0x00010000 /* disable csr drain */
77 #define EBDCSR_BURSTMASK 0x000c0000 /* burst size mask */
78 #define EBDCSR_BURST_1 0x00080000 /* burst 1 */
79 #define EBDCSR_BURST_4 0x00000000 /* burst 4 */
80 #define EBDCSR_BURST_8 0x00040000 /* burst 8 */
81 #define EBDCSR_BURST_16 0x000c0000 /* burst 16 */
82 #define EBDCSR_DIAGEN 0x00100000 /* enable diagnostics */
83 #define EBDCSR_ERRDIS 0x00400000 /* disable error pending */
84 #define EBDCSR_TCIDIS 0x00800000 /* disable TCI */
85 #define EBDCSR_NEXTEN 0x01000000 /* enable next */
86 #define EBDCSR_DMAON 0x02000000 /* dma on */
87 #define EBDCSR_A_LOADED 0x04000000 /* address loaded */
88 #define EBDCSR_NA_LOADED 0x08000000 /* next address loaded */
89 #define EBDCSR_DEVMASK 0xf0000000 /* device id mask */