2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Berkeley Software Design Inc's name may not be used to endorse or
15 * promote products derived from this software without specific prior
18 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: BSDI: asi.h,v 1.3 1997/08/08 14:31:42 torek
34 #ifndef _MACHINE_ASI_H_
35 #define _MACHINE_ASI_H_
44 #define ASI_AIUPL 0x18
45 #define ASI_AIUSL 0x19
56 * UltraSPARC extensions - ASIs limited to a certain family are annotated.
58 #define ASI_PHYS_USE_EC 0x14
59 #define ASI_PHYS_BYPASS_EC_WITH_EBIT 0x15
60 #define ASI_PHYS_USE_EC_L 0x1c
61 #define ASI_PHYS_BYPASS_EC_WITH_EBIT_L 0x1d
63 #define ASI_NUCLEUS_QUAD_LDD 0x24
64 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c
66 #define ASI_PCACHE_STATUS_DATA 0x30 /* US-III Cu */
67 #define ASI_PCACHE_DATA 0x31 /* US-III Cu */
68 #define ASI_PCACHE_TAG 0x32 /* US-III Cu */
69 #define ASI_PCACHE_SNOOP_TAG 0x33 /* US-III Cu */
71 #define ASI_ATOMIC_QUAD_LDD_PHYS 0x34 /* US-III Cu */
73 #define ASI_WCACHE_VALID_BITS 0x38 /* US-III Cu */
74 #define ASI_WCACHE_DATA 0x39 /* US-III Cu */
75 #define ASI_WCACHE_TAG 0x3a /* US-III Cu */
76 #define ASI_WCACHE_SNOOP_TAG 0x3b /* US-III Cu */
78 #define ASI_ATOMIC_QUAD_LDD_PHYS_L 0x3c /* US-III Cu */
80 #define ASI_SRAM_FAST_INIT 0x40 /* US-III Cu */
82 #define ASI_DCACHE_INVALIDATE 0x42 /* US-III Cu */
83 #define ASI_DCACHE_UTAG 0x43 /* US-III Cu */
84 #define ASI_DCACHE_SNOOP_TAG 0x44 /* US-III Cu */
86 /* Named ASI_DCUCR on US-III, but is mostly identical except for added bits. */
87 #define ASI_LSU_CTL_REG 0x45 /* US only */
89 #define ASI_MCNTL 0x45 /* SPARC64 only */
92 #define ASI_DCACHE_DATA 0x46
93 #define ASI_DCACHE_TAG 0x47
95 #define ASI_INTR_DISPATCH_STATUS 0x48
96 #define ASI_INTR_RECEIVE 0x49
97 #define ASI_UPA_CONFIG_REG 0x4a /* US-I, II */
99 #define ASI_FIREPLANE_CONFIG_REG 0x4a /* US-III{,+}, IV{,+} */
100 #define AA_FIREPLANE_CONFIG 0x0 /* US-III{,+}, IV{,+} */
101 #define AA_FIREPLANE_ADDRESS 0x8 /* US-III{,+}, IV{,+} */
102 #define AA_FIREPLANE_CONFIG_2 0x10 /* US-IV{,+} */
104 #define ASI_JBUS_CONFIG_REG 0x4a /* US-IIIi{,+} */
106 #define ASI_ESTATE_ERROR_EN_REG 0x4b
107 #define AA_ESTATE_CEEN 0x1
108 #define AA_ESTATE_NCEEN 0x2
109 #define AA_ESTATE_ISAPEN 0x4
111 #define ASI_AFSR 0x4c
112 #define ASI_AFAR 0x4d
114 #define ASI_ECACHE_TAG_DATA 0x4e
116 #define ASI_IMMU_TAG_TARGET_REG 0x50
117 #define ASI_IMMU 0x50
118 #define AA_IMMU_TTR 0x0
119 #define AA_IMMU_SFSR 0x18
120 #define AA_IMMU_TSB 0x28
121 #define AA_IMMU_TAR 0x30
122 #define AA_IMMU_TSB_PEXT_REG 0x48 /* US-III family */
123 #define AA_IMMU_TSB_SEXT_REG 0x50 /* US-III family */
124 #define AA_IMMU_TSB_NEXT_REG 0x58 /* US-III family */
126 #define ASI_IMMU_TSB_8KB_PTR_REG 0x51
127 #define ASI_IMMU_TSB_64KB_PTR_REG 0x52
129 #define ASI_SERIAL_ID 0x53 /* US-III family */
131 #define ASI_ITLB_DATA_IN_REG 0x54
132 /* US-III Cu: also ASI_ITLB_CAM_ADDRESS_REG */
133 #define ASI_ITLB_DATA_ACCESS_REG 0x55
134 #define ASI_ITLB_TAG_READ_REG 0x56
135 #define ASI_IMMU_DEMAP 0x57
137 #define ASI_DMMU_TAG_TARGET_REG 0x58
138 #define ASI_DMMU 0x58
139 #define AA_DMMU_TTR 0x0
140 #define AA_DMMU_PCXR 0x8
141 #define AA_DMMU_SCXR 0x10
142 #define AA_DMMU_SFSR 0x18
143 #define AA_DMMU_SFAR 0x20
144 #define AA_DMMU_TSB 0x28
145 #define AA_DMMU_TAR 0x30
146 #define AA_DMMU_VWPR 0x38
147 #define AA_DMMU_PWPR 0x40
148 #define AA_DMMU_TSB_PEXT_REG 0x48
149 #define AA_DMMU_TSB_SEXT_REG 0x50
150 #define AA_DMMU_TSB_NEXT_REG 0x58
151 #define AA_DMMU_TAG_ACCESS_EXT 0x60 /* US-III family */
153 #define ASI_DMMU_TSB_8KB_PTR_REG 0x59
154 #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
155 #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
156 #define ASI_DTLB_DATA_IN_REG 0x5c
157 /* US-III Cu: also ASI_DTLB_CAM_ADDRESS_REG */
158 #define ASI_DTLB_DATA_ACCESS_REG 0x5d
159 #define ASI_DTLB_TAG_READ_REG 0x5e
160 #define ASI_DMMU_DEMAP 0x5f
162 #define ASI_IIU_INST_TRAP 0x60 /* US-III family */
164 #define ASI_INTR_ID 0x63 /* US-IV{,+} */
165 #define AA_INTR_ID 0x0 /* US-IV{,+} */
166 #define AA_CORE_ID 0x10 /* US-IV{,+} */
167 #define AA_CESR_ID 0x40 /* US-IV{,+} */
169 #define ASI_ICACHE_INSTR 0x66
170 #define ASI_ICACHE_TAG 0x67
171 #define ASI_ICACHE_SNOOP_TAG 0x68 /* US-III family */
172 #define ASI_ICACHE_PRE_DECODE 0x6e /* US-I, II */
173 #define ASI_ICACHE_PRE_NEXT_FIELD 0x6f /* US-I, II */
175 #define ASI_FLUSH_L1I 0x67 /* SPARC64 only */
177 #define ASI_BLK_AUIP 0x70
178 #define ASI_BLK_AIUS 0x71
180 #define ASI_MCU_CONFIG_REG 0x72 /* US-III Cu */
181 #define AA_MCU_TIMING1_REG 0x0 /* US-III Cu */
182 #define AA_MCU_TIMING2_REG 0x8 /* US-III Cu */
183 #define AA_MCU_TIMING3_REG 0x10 /* US-III Cu */
184 #define AA_MCU_TIMING4_REG 0x18 /* US-III Cu */
185 #define AA_MCU_DEC1_REG 0x20 /* US-III Cu */
186 #define AA_MCU_DEC2_REG 0x28 /* US-III Cu */
187 #define AA_MCU_DEC3_REG 0x30 /* US-III Cu */
188 #define AA_MCU_DEC4_REG 0x38 /* US-III Cu */
189 #define AA_MCU_ADDR_CNTL_REG 0x40 /* US-III Cu */
191 #define ASI_ECACHE_DATA 0x74 /* US-III Cu */
192 #define ASI_ECACHE_CONTROL 0x75 /* US-III Cu */
193 #define ASI_ECACHE_W 0x76
196 * With the advent of the US-III, the numbering has changed, as additional
197 * registers were inserted in between. We retain the original ordering for
198 * now, and append an A to the inserted registers.
199 * Exceptions are AA_SDB_INTR_D6 and AA_SDB_INTR_D7, which were appended
202 #define ASI_SDB_ERROR_W 0x77
203 #define ASI_SDB_CONTROL_W 0x77
204 #define ASI_SDB_INTR_W 0x77
205 #define AA_SDB_ERR_HIGH 0x0
206 #define AA_SDB_ERR_LOW 0x18
207 #define AA_SDB_CNTL_HIGH 0x20
208 #define AA_SDB_CNTL_LOW 0x38
209 #define AA_SDB_INTR_D0 0x40
210 #define AA_SDB_INTR_D0A 0x48 /* US-III family */
211 #define AA_SDB_INTR_D1 0x50
212 #define AA_SDB_INTR_D1A 0x5A /* US-III family */
213 #define AA_SDB_INTR_D2 0x60
214 #define AA_SDB_INTR_D2A 0x68 /* US-III family */
215 #define AA_INTR_SEND 0x70
216 #define AA_SDB_INTR_D6 0x80 /* US-III family */
217 #define AA_SDB_INTR_D7 0x88 /* US-III family */
219 #define ASI_BLK_AIUPL 0x78
220 #define ASI_BLK_AIUSL 0x79
222 #define ASI_ECACHE_R 0x7e
225 * These have the same registers as their corresponding write versions
226 * except for AA_INTR_SEND.
228 #define ASI_SDB_ERROR_R 0x7f
229 #define ASI_SDB_CONTROL_R 0x7f
230 #define ASI_SDB_INTR_R 0x7f
232 #define ASI_PST8_P 0xc0
233 #define ASI_PST8_S 0xc1
234 #define ASI_PST16_P 0xc2
235 #define ASI_PST16_S 0xc3
236 #define ASI_PST32_P 0xc4
237 #define ASI_PST32_S 0xc5
239 #define ASI_PST8_PL 0xc8
240 #define ASI_PST8_SL 0xc9
241 #define ASI_PST16_PL 0xca
242 #define ASI_PST16_SL 0xcb
243 #define ASI_PST32_PL 0xcc
244 #define ASI_PST32_SL 0xcd
246 #define ASI_FL8_P 0xd0
247 #define ASI_FL8_S 0xd1
248 #define ASI_FL16_P 0xd2
249 #define ASI_FL16_S 0xd3
250 #define ASI_FL8_PL 0xd8
251 #define ASI_FL8_SL 0xd9
252 #define ASI_FL16_PL 0xda
253 #define ASI_FL16_SL 0xdb
255 #define ASI_BLK_COMMIT_P 0xe0
256 #define ASI_BLK_COMMIT_S 0xe1
257 #define ASI_BLK_P 0xf0
258 #define ASI_BLK_S 0xf1
259 #define ASI_BLK_PL 0xf8
260 #define ASI_BLK_SL 0xf9
262 #endif /* !_MACHINE_ASI_H_ */