2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2001 Jake Burkholder.
5 * Copyright (c) 2011 Marius Strobl <marius@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _MACHINE_ASMACROS_H_
33 #define _MACHINE_ASMACROS_H_
38 * Normal and alternate %g6 point to the pcb of the current process. Normal,
39 * alternate and interrupt %g7 point to per-cpu data.
45 * Alternate %g5 points to a per-cpu panic stack, which is used as a last
46 * resort, and for temporarily saving alternate globals.
53 * Atomically decrement an integer in memory.
55 #define ATOMIC_DEC_INT(r1, r2, r3) \
58 casa [r1] ASI_N, r2, r3 ; \
64 * Atomically increment an integer in memory.
66 #define ATOMIC_INC_INT(r1, r2, r3) \
69 casa [r1] ASI_N, r2, r3 ; \
75 * Atomically increment a long in memory.
77 #define ATOMIC_INC_LONG(r1, r2, r3) \
80 casxa [r1] ASI_N, r2, r3 ; \
86 * Atomically clear a number of bits of an integer in memory.
88 #define ATOMIC_CLEAR_INT(r1, r2, r3, bits) \
90 9: andn r2, bits, r3 ; \
91 casa [r1] ASI_N, r2, r3 ; \
97 * Atomically clear a number of bits of a long in memory.
99 #define ATOMIC_CLEAR_LONG(r1, r2, r3, bits) \
101 9: andn r2, bits, r3 ; \
102 casxa [r1] ASI_N, r2, r3 ; \
108 * Atomically load an integer from memory.
110 #define ATOMIC_LOAD_INT(r1, val) \
112 casa [r1] ASI_N, %g0, val
115 * Atomically load a long from memory.
117 #define ATOMIC_LOAD_LONG(r1, val) \
119 casxa [r1] ASI_N, %g0, val
122 * Atomically set a number of bits of an integer in memory.
124 #define ATOMIC_SET_INT(r1, r2, r3, bits) \
126 9: or r2, bits, r3 ; \
127 casa [r1] ASI_N, r2, r3 ; \
133 * Atomically set a number of bits of a long in memory.
135 #define ATOMIC_SET_LONG(r1, r2, r3, bits) \
137 9: or r2, bits, r3 ; \
138 casxa [r1] ASI_N, r2, r3 ; \
144 * Atomically store an integer in memory.
146 #define ATOMIC_STORE_INT(r1, r2, r3, val) \
149 casa [r1] ASI_N, r2, r3 ; \
155 * Atomically store a long in memory.
157 #define ATOMIC_STORE_LONG(r1, r2, r3, val) \
160 casxa [r1] ASI_N, r2, r3 ; \
165 #define PCPU(member) PCPU_REG + PC_ ## member
166 #define PCPU_ADDR(member, reg) \
167 add PCPU_REG, PC_ ## member, reg
172 #define PANIC(msg, r1) \
181 #define KASSERT(r1, msg) \
187 #define KASSERT(r1, msg)
190 #define PUTS(msg, r1) \
198 #define _ALIGN_DATA .align 8
204 .type name, @object ; \
210 * Generate atomic compare and swap, load and store instructions for the
211 * corresponding width and ASI (or not). Note that we want to evaluate the
212 * macro args before concatenating, so that EMPTY really turns into nothing.
214 #define _LD(w, a) ld ## w ## a
215 #define _ST(w, a) st ## w ## a
216 #define _CAS(w, a) cas ## w ## a
218 #define LD(w, a) _LD(w, a)
219 #define ST(w, a) _ST(w, a)
220 #define CAS(w, a) _CAS(w, a)
226 #endif /* !_MACHINE_ASMACROS_H_ */