2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * form: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
39 #ifndef _MACHINE_BUS_COMMON_H_
40 #define _MACHINE_BUS_COMMON_H_
42 #define INTCLR_PENDING 0x000000003ULL /* Interrupt queued to CPU */
43 #define INTCLR_RECEIVED 0x000000001ULL /* Interrupt received */
44 #define INTCLR_IDLE 0x000000000ULL /* Interrupt idle */
46 #define INTMAP_V 0x080000000ULL /* Interrupt valid (enabled) */
47 #define INTMAP_TID_MASK 0x07c000000ULL /* UPA target ID */
48 #define INTMAP_TID_SHIFT 26
49 #define INTMAP_IGN_MASK 0x0000007c0ULL /* Interrupt group no. */
50 #define INTMAP_IGN_SHIFT 6
51 #define INTMAP_INO_MASK 0x00000003fULL /* Interrupt number */
52 #define INTMAP_INR_MASK (INTMAP_IGN_MASK | INTMAP_INO_MASK)
53 #define INTMAP_SBUSSLOT_MASK 0x000000018ULL /* SBus slot # */
54 #define INTMAP_PCIBUS_MASK 0x000000010ULL /* PCI bus number (A or B) */
55 #define INTMAP_PCISLOT_MASK 0x00000000cULL /* PCI slot # */
56 #define INTMAP_PCIINT_MASK 0x000000003ULL /* PCI interrupt #A,#B,#C,#D */
57 #define INTMAP_OBIO_MASK 0x000000020ULL /* Onboard device */
58 #define INTIGN(x) (((x) & INTMAP_IGN_MASK) >> INTMAP_IGN_SHIFT)
59 #define INTVEC(x) ((x) & INTMAP_INR_MASK)
60 #define INTSLOT(x) (((x) >> 3) & 0x7)
61 #define INTPRI(x) ((x) & 0x7)
62 #define INTINO(x) ((x) & INTMAP_INO_MASK)
63 #define INTMAP_ENABLE(mr, mid) \
64 (INTMAP_TID((mr), (mid)) | INTMAP_V)
65 #define INTMAP_TID(mr, mid) \
66 (((mr) & ~INTMAP_TID_MASK) | ((mid) << INTMAP_TID_SHIFT))
67 #define INTMAP_VEC(ign, ino) \
68 ((((ign) << INTMAP_IGN_SHIFT) & INTMAP_IGN_MASK) | \
69 ((ino) & INTMAP_INO_MASK))
71 /* counter-timer support. */
72 void sparc64_counter_init(const char *name, bus_space_tag_t tag,
73 bus_space_handle_t handle, bus_addr_t offset);
75 #endif /* !_MACHINE_BUS_COMMON_H_ */