2 * Copyright (c) 2001 Jake Burkholder.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_CPUFUNC_H_
30 #define _MACHINE_CPUFUNC_H_
32 #include <machine/asi.h>
33 #include <machine/pstate.h>
36 * membar operand macros for use in other macros when # is a special
37 * character. Keep these in sync with what the hardware expects.
39 #define C_Lookaside (0)
40 #define C_MemIssue (1)
42 #define M_LoadLoad (0)
43 #define M_StoreLoad (1)
44 #define M_LoadStore (2)
45 #define M_StoreStore (3)
47 #define CMASK_SHIFT (4)
48 #define MMASK_SHIFT (0)
50 #define CMASK_GEN(bit) ((1 << (bit)) << CMASK_SHIFT)
51 #define MMASK_GEN(bit) ((1 << (bit)) << MMASK_SHIFT)
53 #define Lookaside CMASK_GEN(C_Lookaside)
54 #define MemIssue CMASK_GEN(C_MemIssue)
55 #define Sync CMASK_GEN(C_Sync)
56 #define LoadLoad MMASK_GEN(M_LoadLoad)
57 #define StoreLoad MMASK_GEN(M_StoreLoad)
58 #define LoadStore MMASK_GEN(M_LoadStore)
59 #define StoreStore MMASK_GEN(M_StoreStore)
61 #define casa(rs1, rs2, rd, asi) ({ \
62 u_int __rd = (u_int32_t)(rd); \
63 __asm __volatile("casa [%1] %2, %3, %0" \
64 : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2)); \
68 #define casxa(rs1, rs2, rd, asi) ({ \
69 u_long __rd = (u_int64_t)(rd); \
70 __asm __volatile("casxa [%1] %2, %3, %0" \
71 : "+r" (__rd) : "r" (rs1), "n" (asi), "r" (rs2)); \
75 #define flush(va) do { \
76 __asm __volatile("flush %0" : : "r" (va)); \
79 #define flushw() do { \
80 __asm __volatile("flushw" : :); \
83 #define mov(val, reg) do { \
84 __asm __volatile("mov %0, %" __XSTRING(reg) : : "r" (val)); \
87 /* Generate ld*a/st*a functions for non-constant ASI's. */
88 #define LDNC_GEN(tp, o) \
90 o ## _nc(caddr_t va, int asi) \
93 __asm __volatile("wr %2, 0, %%asi;" #o " [%1] %%asi, %0"\
94 : "=r" (r) : "r" (va), "r" (asi)); \
98 LDNC_GEN(u_char, lduba);
99 LDNC_GEN(u_short, lduha);
100 LDNC_GEN(u_int, lduwa);
101 LDNC_GEN(u_long, ldxa);
103 #define LD_GENERIC(va, asi, op, type) ({ \
105 __asm __volatile(#op " [%1] %2, %0" \
106 : "=r" (__r) : "r" (va), "n" (asi)); \
110 #define lduba(va, asi) LD_GENERIC(va, asi, lduba, u_char)
111 #define lduha(va, asi) LD_GENERIC(va, asi, lduha, u_short)
112 #define lduwa(va, asi) LD_GENERIC(va, asi, lduwa, u_int)
113 #define ldxa(va, asi) LD_GENERIC(va, asi, ldxa, u_long)
115 #define STNC_GEN(tp, o) \
116 static __inline void \
117 o ## _nc(caddr_t va, int asi, tp val) \
119 __asm __volatile("wr %2, 0, %%asi;" #o " %0, [%1] %%asi"\
120 : : "r" (val), "r" (va), "r" (asi)); \
123 STNC_GEN(u_char, stba);
124 STNC_GEN(u_short, stha);
125 STNC_GEN(u_int, stwa);
126 STNC_GEN(u_long, stxa);
128 #define ST_GENERIC(va, asi, val, op) \
129 __asm __volatile(#op " %0, [%1] %2" \
130 : : "r" (val), "r" (va), "n" (asi)); \
132 #define stba(va, asi, val) ST_GENERIC(va, asi, val, stba)
133 #define stha(va, asi, val) ST_GENERIC(va, asi, val, stha)
134 #define stwa(va, asi, val) ST_GENERIC(va, asi, val, stwa)
135 #define stxa(va, asi, val) ST_GENERIC(va, asi, val, stxa)
137 #define membar(mask) do { \
138 __asm __volatile("membar %0" : : "n" (mask) : "memory"); \
141 #define rd(name) ({ \
143 __asm __volatile("rd %%" #name ", %0" : "=r" (__sr) :); \
147 #define wr(name, val, xor) do { \
148 __asm __volatile("wr %0, %1, %%" #name \
149 : : "r" (val), "rI" (xor)); \
152 #define rdpr(name) ({ \
154 __asm __volatile("rdpr %%" #name", %0" : "=r" (__pr) :); \
158 #define wrpr(name, val, xor) do { \
159 __asm __volatile("wrpr %0, %1, %%" #name \
160 : : "r" (val), "rI" (xor)); \
163 #define CRITICAL_FORK (0)
168 __asm __volatile("ta %%xcc, 1" : :);
171 static __inline critical_t
172 cpu_critical_enter(void)
182 cpu_critical_exit(critical_t pil)
187 static __inline register_t
193 wrpr(pstate, s & ~PSTATE_IE, 0);
196 #define intr_restore(s) wrpr(pstate, (s), 0)
199 * In some places, it is required that the store is directly followed by a
200 * membar #Sync. Don't trust the compiler to not insert instructions in
201 * between. We also need to disable interrupts completely.
203 #define stxa_sync(va, asi, val) do { \
204 u_long s = intr_disable(); \
205 __asm __volatile("stxa %0, [%1] %2; membar #Sync" \
206 : : "r" (val), "r" (va), "n" (asi)); \
210 void ascopy(u_long asi, vm_offset_t src, vm_offset_t dst, size_t len);
211 void ascopyfrom(u_long sasi, vm_offset_t src, caddr_t dst, size_t len);
212 void ascopyto(caddr_t src, u_long dasi, vm_offset_t dst, size_t len);
213 void aszero(u_long asi, vm_offset_t dst, size_t len);
216 * Ultrasparc II doesn't implement popc in hardware. Suck.
219 #define HAVE_INLINE_FFS
221 * See page 202 of the SPARC v9 Architecture Manual.
232 " xnor %3, %1, %2 ; "
234 " movrz %3, %%g0, %0 ; "
235 : "=r" (result), "=r" (neg), "=r" (tmp) : "r" (mask));
243 #endif /* !_MACHINE_CPUFUNC_H_ */