2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This software was developed by the Computer Systems Engineering group
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9 * contributed to Berkeley.
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12 * modification, are permitted provided that the following conditions
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35 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
36 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
41 #ifndef _MACHINE_IOMMUREG_H_
42 #define _MACHINE_IOMMUREG_H_
45 * UltraSPARC IOMMU registers, common to both the PCI and SBus
50 #define IMR_CTL 0x0000 /* IOMMU control register */
51 #define IMR_TSB 0x0008 /* IOMMU TSB base register */
52 #define IMR_FLUSH 0x0010 /* IOMMU flush register */
53 /* The TTE Cache is Fire and Oberon only. */
54 #define IMR_CACHE_FLUSH 0x0100 /* IOMMU TTE cache flush address register */
55 #define IMR_CACHE_INVAL 0x0108 /* IOMMU TTE cache invalidate register */
57 /* streaming buffer registers */
58 #define ISR_CTL 0x0000 /* streaming buffer control reg */
59 #define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */
60 #define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */
62 /* streaming buffer diagnostics registers */
63 #define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */
64 #define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */
65 #define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */
66 #define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */
68 /* streaming buffer control register */
69 #define STRBUF_EN 0x0000000000000001UL
70 #define STRBUF_D 0x0000000000000002UL
71 #define STRBUF_RR_DIS 0x0000000000000004UL
73 #define IOMMU_MAXADDR(bits) ((1UL << (bits)) - 1)
76 * control register bits
78 /* Nummber of entries in the IOTSB - pre-Fire only */
79 #define IOMMUCR_TSBSZ_MASK 0x0000000000070000UL
80 #define IOMMUCR_TSBSZ_SHIFT 16
81 /* TSB cache snoop enable */
82 #define IOMMUCR_SE 0x0000000000000400UL
83 /* Cache modes - Fire and Oberon */
84 #define IOMMUCR_CM_NC_TLB_TBW 0x0000000000000000UL
85 #define IOMMUCR_CM_LC_NTLB_NTBW 0x0000000000000100UL
86 #define IOMMUCR_CM_LC_TLB_TBW 0x0000000000000200UL
87 #define IOMMUCR_CM_C_TLB_TBW 0x0000000000000300UL
88 /* IOMMU page size - pre-Fire only */
89 #define IOMMUCR_8KPG 0x0000000000000000UL
90 #define IOMMUCR_64KPG 0x0000000000000004UL
91 /* Bypass enable - Fire and Oberon */
92 #define IOMMUCR_BE 0x0000000000000002UL
93 /* Diagnostic mode enable - pre-Fire only */
94 #define IOMMUCR_DE 0x0000000000000002UL
95 /* IOMMU/translation enable */
96 #define IOMMUCR_EN 0x0000000000000001UL
99 * TSB base register bits
101 /* TSB base address */
102 #define IOMMUTB_TB_MASK 0x000007ffffffe000UL
103 #define IOMMUTB_TB_SHIFT 13
104 /* IOMMU page size - Fire and Oberon */
105 #define IOMMUTB_8KPG 0x0000000000000000UL
106 #define IOMMUTB_64KPG 0x0000000000000100UL
107 /* Nummber of entries in the IOTSB - Fire and Oberon */
108 #define IOMMUTB_TSBSZ_MASK 0x0000000000000004UL
109 #define IOMMUTB_TSBSZ_SHIFT 0
112 * TSB size definitions for both control and TSB base register */
113 #define IOMMU_TSB1K 0
114 #define IOMMU_TSB2K 1
115 #define IOMMU_TSB4K 2
116 #define IOMMU_TSB8K 3
117 #define IOMMU_TSB16K 4
118 #define IOMMU_TSB32K 5
119 #define IOMMU_TSB64K 6
120 #define IOMMU_TSB128K 7
121 /* Fire and Oberon */
122 #define IOMMU_TSB256K 8
123 /* Fire and Oberon */
124 #define IOMMU_TSB512K 9
125 #define IOMMU_TSBENTRIES(tsbsz) \
126 ((1 << (tsbsz)) << (IO_PAGE_SHIFT - IOTTE_SHIFT))
129 * Diagnostic register definitions
131 #define IOMMU_DTAG_VPNBITS 19
132 #define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1)
133 #define IOMMU_DTAG_VPNSHIFT 13
134 #define IOMMU_DTAG_ERRBITS 3
135 #define IOMMU_DTAG_ERRSHIFT 22
136 #define IOMMU_DTAG_ERRMASK \
137 (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT)
139 #define IOMMU_DDATA_PGBITS 21
140 #define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1)
141 #define IOMMU_DDATA_PGSHIFT 13
142 #define IOMMU_DDATA_C (1 << 28)
143 #define IOMMU_DDATA_V (1 << 30)
149 #define IOTTE_V 0x8000000000000000UL
150 /* Page size - pre-Fire only */
151 #define IOTTE_64K 0x2000000000000000UL
152 #define IOTTE_8K 0x0000000000000000UL
153 /* Streamable page - streaming buffer equipped variants only */
154 #define IOTTE_STREAM 0x1000000000000000UL
155 /* Accesses to the same bus segment - SBus only */
156 #define IOTTE_LOCAL 0x0800000000000000UL
157 /* Physical address mask (based on Oberon) */
158 #define IOTTE_PAMASK 0x00007fffffffe000UL
159 /* Accesses to cacheable space - pre-Fire only */
160 #define IOTTE_C 0x0000000000000010UL
162 #define IOTTE_W 0x0000000000000002UL
164 /* log2 of the IOMMU TTE size */
165 #define IOTTE_SHIFT 3
167 /* Streaming buffer line size */
168 #define STRBUF_LINESZ 64
171 * Number of bytes written by a stream buffer flushsync operation to indicate
174 #define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ
177 * On sun4u each bus controller has a separate IOMMU. The IOMMU has
178 * a TSB which must be page aligned and physically contiguous. Mappings
179 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
180 * with the CPU's MMU.
182 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
183 * following size segments:
185 * VA size VA base TSB size tsbsize
186 * -------- -------- --------- -------
188 * 16MB ff000000 16K 1
189 * 32MB fe000000 32K 2
190 * 64MB fc000000 64K 3
191 * 128MB f8000000 128K 4
192 * 256MB f0000000 256K 5
193 * 512MB e0000000 512K 6
196 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
197 * this scheme to determine the IOVA base address. Instead, bits 31-29 are
198 * used to check against the Target Address Space register in the IIi and
199 * the IOMMU is used if they hit. God knows what goes on in the IIe.
203 #define IOTSB_BASESZ (1024 << IOTTE_SHIFT)
204 #define IOTSB_VEND (~IO_PAGE_MASK)
205 #define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10))
207 #define MAKEIOTTE(pa, w, c, s) \
208 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \
209 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \
210 (IOTTE_V | IOTTE_8K))
211 #define IOTSBSLOT(va) \
212 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT)
214 #endif /* !_MACHINE_IOMMUREG_H_ */