2 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
20 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
22 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #ifndef _MACHINE_LSU_H_
28 #define _MACHINE_LSU_H_
31 * Definitions for the Load-Store-Unit Control Register. This is called
32 * Data Cache Unit Control Register (DCUCR) for UltraSPARC-III.
34 #define LSU_IC (1UL << 0)
35 #define LSU_DC (1UL << 1)
36 #define LSU_IM (1UL << 2)
37 #define LSU_DM (1UL << 3)
39 /* Parity control mask, UltraSPARC-I and II series only. */
40 #define LSU_FM_SHIFT 4
41 #define LSU_FM_BITS 16
42 #define LSU_FM_MASK (((1UL << LSU_FM_BITS) - 1) << LSU_FM_SHIFT)
44 #define LSU_VM_SHIFT 25
46 #define LSU_VM_MASK (((1UL << LSU_VM_BITS) - 1) << LSU_VM_SHIFT)
48 #define LSU_PM_SHIFT 33
50 #define LSU_PM_MASK (((1UL << LSU_PM_BITS) - 1) << LSU_PM_SHIFT)
52 #define LSU_VW (1UL << 21)
53 #define LSU_VR (1UL << 22)
54 #define LSU_PW (1UL << 23)
55 #define LSU_PR (1UL << 24)
57 /* The following bits are valid for the UltraSPARC-III series only. */
58 #define LSU_WE (1UL << 41)
59 #define LSU_SL (1UL << 42)
60 #define LSU_SPE (1UL << 43)
61 #define LSU_HPE (1UL << 44)
62 #define LSU_PE (1UL << 45)
63 #define LSU_RE (1UL << 46)
64 #define LSU_ME (1UL << 47)
65 #define LSU_CV (1UL << 48)
66 #define LSU_CP (1UL << 49)
68 #endif /* _MACHINE_LSU_H_ */