2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1990 The Regents of the University of California.
7 * This code is derived from software contributed to Berkeley by
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11 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
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19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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31 * from: @(#)param.h 5.8 (Berkeley) 6/28/91
35 #ifndef _SPARC64_INCLUDE_PARAM_H_
36 #define _SPARC64_INCLUDE_PARAM_H_
39 * Machine dependent constants for sparc64.
42 #include <machine/_align.h>
44 #define __PCI_BAR_ZERO_VALID
47 #define MACHINE "sparc64"
50 #define MACHINE_ARCH "sparc64"
52 #define MID_MACHINE MID_SPARC64
54 #if defined(SMP) || defined(KLD_MODULE)
60 #endif /* SMP || KLD_MODULE */
69 #define ALIGNBYTES _ALIGNBYTES
70 #define ALIGN(p) _ALIGN(p)
72 * ALIGNED_POINTER is a boolean macro that checks whether an address
73 * is valid to fetch data elements of type t from on this architecture.
74 * This does not reflect the optimal alignment, just the possibility
75 * (within reasonable limits).
77 #define ALIGNED_POINTER(p, t) ((((u_long)(p)) & (sizeof (t) - 1)) == 0)
80 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
81 * architecture. It should be used with appropriate caution.
83 #define CACHE_LINE_SHIFT 7
84 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
86 #define PAGE_SHIFT_8K 13
87 #define PAGE_SIZE_8K (1L<<PAGE_SHIFT_8K)
88 #define PAGE_MASK_8K (PAGE_SIZE_8K-1)
90 #define PAGE_SHIFT_64K 16
91 #define PAGE_SIZE_64K (1L<<PAGE_SHIFT_64K)
92 #define PAGE_MASK_64K (PAGE_SIZE_64K-1)
94 #define PAGE_SHIFT_512K 19
95 #define PAGE_SIZE_512K (1L<<PAGE_SHIFT_512K)
96 #define PAGE_MASK_512K (PAGE_SIZE_512K-1)
98 #define PAGE_SHIFT_4M 22
99 #define PAGE_SIZE_4M (1L<<PAGE_SHIFT_4M)
100 #define PAGE_MASK_4M (PAGE_SIZE_4M-1)
102 #define PAGE_SHIFT_32M 25
103 #define PAGE_SIZE_32M (1L<<PAGE_SHIFT_32M)
104 #define PAGE_MASK_32M (PAGE_SIZE_32M-1)
106 #define PAGE_SHIFT_256M 28
107 #define PAGE_SIZE_256M (1L<<PAGE_SHIFT_256M)
108 #define PAGE_MASK_256M (PAGE_SIZE_256M-1)
110 #define PAGE_SHIFT_MIN PAGE_SHIFT_8K
111 #define PAGE_SIZE_MIN PAGE_SIZE_8K
112 #define PAGE_MASK_MIN PAGE_MASK_8K
113 #define PAGE_SHIFT PAGE_SHIFT_8K /* LOG2(PAGE_SIZE) */
114 #define PAGE_SIZE PAGE_SIZE_8K /* bytes/page */
115 #define PAGE_MASK PAGE_MASK_8K
116 #define PAGE_SHIFT_MAX PAGE_SHIFT_4M
117 #define PAGE_SIZE_MAX PAGE_SIZE_4M
118 #define PAGE_MASK_MAX PAGE_MASK_4M
120 #define MAXPAGESIZES 1 /* maximum number of supported page sizes */
123 #define KSTACK_PAGES 4 /* pages of kernel stack (with pcb) */
125 #define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
129 * Ceiling on size of buffer cache (really only effects write queueing,
130 * the VM page cache is not effected), can be changed via
131 * the kern.maxbcache /boot/loader.conf variable.
133 #ifndef VM_BCACHE_SIZE_MAX
134 #define VM_BCACHE_SIZE_MAX (400 * 1024 * 1024)
138 * Mach derived conversion macros
140 #define round_page(x) (((unsigned long)(x) + PAGE_MASK) & ~PAGE_MASK)
141 #define trunc_page(x) ((unsigned long)(x) & ~PAGE_MASK)
143 #define atop(x) ((unsigned long)(x) >> PAGE_SHIFT)
144 #define ptoa(x) ((unsigned long)(x) << PAGE_SHIFT)
146 #define sparc64_btop(x) ((unsigned long)(x) >> PAGE_SHIFT)
147 #define sparc64_ptob(x) ((unsigned long)(x) << PAGE_SHIFT)
149 #define pgtok(x) ((unsigned long)(x) * (PAGE_SIZE / 1024))
155 #endif /* !_SPARC64_INCLUDE_PARAM_H_ */