2 * Copyright (c) 2001 Jake Burkholder.
3 * Copyright (c) 2007 - 2011 Marius Strobl <marius@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #ifndef _MACHINE_SMP_H_
31 #define _MACHINE_SMP_H_
35 #define CPU_TICKSYNC 1
36 #define CPU_STICKSYNC 2
38 #define CPU_BOOTSTRAP 4
42 #include <sys/cpuset.h>
44 #include <sys/sched.h>
47 #include <machine/intr_machdep.h>
48 #include <machine/pcb.h>
49 #include <machine/tte.h>
51 #define IDR_BUSY 0x0000000000000001ULL
52 #define IDR_NACK 0x0000000000000002ULL
53 #define IDR_CHEETAH_ALL_BUSY 0x5555555555555555ULL
54 #define IDR_CHEETAH_ALL_NACK (~IDR_CHEETAH_ALL_BUSY)
55 #define IDR_CHEETAH_MAX_BN_PAIRS 32
56 #define IDR_JALAPENO_MAX_BN_PAIRS 4
58 #define IDC_ITID_SHIFT 14
59 #define IDC_BN_SHIFT 24
61 #define IPI_AST PIL_AST
62 #define IPI_RENDEZVOUS PIL_RENDEZVOUS
63 #define IPI_PREEMPT PIL_PREEMPT
64 #define IPI_HARDCLOCK PIL_HARDCLOCK
65 #define IPI_STOP PIL_STOP
66 #define IPI_STOP_HARD PIL_STOP
68 #define IPI_RETRIES 5000
70 struct cpu_start_args {
78 struct tte csa_ttes[PCPU_PAGES];
81 struct ipi_cache_args {
93 struct pmap *ita_pmap;
97 #define ita_va ita_start
101 extern struct pcb stoppcbs[];
103 void cpu_mp_bootstrap(struct pcpu *pc);
104 void cpu_mp_shutdown(void);
106 typedef void cpu_ipi_selected_t(cpuset_t, u_long, u_long, u_long);
107 extern cpu_ipi_selected_t *cpu_ipi_selected;
108 typedef void cpu_ipi_single_t(u_int, u_long, u_long, u_long);
109 extern cpu_ipi_single_t *cpu_ipi_single;
111 void mp_init(u_int cpu_impl);
113 extern struct ipi_cache_args ipi_cache_args;
114 extern struct ipi_rd_args ipi_rd_args;
115 extern struct ipi_tlb_args ipi_tlb_args;
117 extern char *mp_tramp_code;
118 extern u_long mp_tramp_code_len;
119 extern u_long mp_tramp_tlb_slots;
120 extern u_long mp_tramp_func;
122 extern void mp_startup(void);
124 extern char tl_ipi_cheetah_dcache_page_inval[];
125 extern char tl_ipi_spitfire_dcache_page_inval[];
126 extern char tl_ipi_spitfire_icache_page_inval[];
128 extern char tl_ipi_level[];
130 extern char tl_ipi_stick_rd[];
131 extern char tl_ipi_tick_rd[];
133 extern char tl_ipi_tlb_context_demap[];
134 extern char tl_ipi_tlb_page_demap[];
135 extern char tl_ipi_tlb_range_demap[];
138 ipi_all_but_self(u_int ipi)
143 CPU_CLR(PCPU_GET(cpuid), &cpus);
144 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
148 ipi_selected(cpuset_t cpus, u_int ipi)
151 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
155 ipi_cpu(int cpu, u_int ipi)
158 cpu_ipi_single(cpu, 0, (u_long)tl_ipi_level, ipi);
161 #if defined(_MACHINE_PMAP_H_) && defined(_SYS_MUTEX_H_)
163 static __inline void *
164 ipi_dcache_page_inval(void *func, vm_paddr_t pa)
166 struct ipi_cache_args *ica;
171 ica = &ipi_cache_args;
172 mtx_lock_spin(&smp_ipi_mtx);
173 ica->ica_mask = all_cpus;
174 CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
176 cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
177 return (&ica->ica_mask);
180 static __inline void *
181 ipi_icache_page_inval(void *func, vm_paddr_t pa)
183 struct ipi_cache_args *ica;
188 ica = &ipi_cache_args;
189 mtx_lock_spin(&smp_ipi_mtx);
190 ica->ica_mask = all_cpus;
191 CPU_CLR(PCPU_GET(cpuid), &ica->ica_mask);
193 cpu_ipi_selected(ica->ica_mask, 0, (u_long)func, (u_long)ica);
194 return (&ica->ica_mask);
197 static __inline void *
198 ipi_rd(u_int cpu, void *func, u_long *val)
200 struct ipi_rd_args *ira;
206 mtx_lock_spin(&smp_ipi_mtx);
207 CPU_SETOF(cpu, &ira->ira_mask);
209 cpu_ipi_single(cpu, 0, (u_long)func, (u_long)ira);
210 return (&ira->ira_mask);
213 static __inline void *
214 ipi_tlb_context_demap(struct pmap *pm)
216 struct ipi_tlb_args *ita;
222 cpus = pm->pm_active;
223 CPU_AND(&cpus, &all_cpus);
224 CPU_CLR(PCPU_GET(cpuid), &cpus);
225 if (CPU_EMPTY(&cpus)) {
230 mtx_lock_spin(&smp_ipi_mtx);
231 ita->ita_mask = cpus;
233 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_context_demap,
235 return (&ita->ita_mask);
238 static __inline void *
239 ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
241 struct ipi_tlb_args *ita;
247 cpus = pm->pm_active;
248 CPU_AND(&cpus, &all_cpus);
249 CPU_CLR(PCPU_GET(cpuid), &cpus);
250 if (CPU_EMPTY(&cpus)) {
255 mtx_lock_spin(&smp_ipi_mtx);
256 ita->ita_mask = cpus;
259 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
260 return (&ita->ita_mask);
263 static __inline void *
264 ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
266 struct ipi_tlb_args *ita;
272 cpus = pm->pm_active;
273 CPU_AND(&cpus, &all_cpus);
274 CPU_CLR(PCPU_GET(cpuid), &cpus);
275 if (CPU_EMPTY(&cpus)) {
280 mtx_lock_spin(&smp_ipi_mtx);
281 ita->ita_mask = cpus;
283 ita->ita_start = start;
285 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_range_demap,
287 return (&ita->ita_mask);
291 ipi_wait(void *cookie)
293 volatile cpuset_t *mask;
295 if ((mask = cookie) != NULL) {
296 while (!CPU_EMPTY(mask))
298 mtx_unlock_spin(&smp_ipi_mtx);
303 #endif /* _MACHINE_PMAP_H_ && _SYS_MUTEX_H_ */
311 static __inline void *
312 ipi_dcache_page_inval(void *func __unused, vm_paddr_t pa __unused)
318 static __inline void *
319 ipi_icache_page_inval(void *func __unused, vm_paddr_t pa __unused)
325 static __inline void *
326 ipi_rd(u_int cpu __unused, void *func __unused, u_long *val __unused)
332 static __inline void *
333 ipi_tlb_context_demap(struct pmap *pm __unused)
339 static __inline void *
340 ipi_tlb_page_demap(struct pmap *pm __unused, vm_offset_t va __unused)
346 static __inline void *
347 ipi_tlb_range_demap(struct pmap *pm __unused, vm_offset_t start __unused,
348 __unused vm_offset_t end)
355 ipi_wait(void *cookie __unused)
361 tl_ipi_cheetah_dcache_page_inval(void)
367 tl_ipi_spitfire_dcache_page_inval(void)
373 tl_ipi_spitfire_icache_page_inval(void)
382 #endif /* !_MACHINE_SMP_H_ */