2 * Copyright (c) 2001 Jake Burkholder.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #ifndef _MACHINE_SMP_H_
30 #define _MACHINE_SMP_H_
34 #define CPU_TICKSYNC 1
35 #define CPU_STICKSYNC 2
37 #define CPU_BOOTSTRAP 4
41 #include <machine/intr_machdep.h>
42 #include <machine/pcb.h>
43 #include <machine/tte.h>
45 #define IDR_BUSY 0x0000000000000001ULL
46 #define IDR_NACK 0x0000000000000002ULL
47 #define IDR_CHEETAH_ALL_BUSY 0x5555555555555555ULL
48 #define IDR_CHEETAH_ALL_NACK (~IDR_CHEETAH_ALL_BUSY)
49 #define IDR_CHEETAH_MAX_BN_PAIRS 32
50 #define IDR_JALAPENO_MAX_BN_PAIRS 4
52 #define IDC_ITID_SHIFT 14
53 #define IDC_BN_SHIFT 24
55 #define IPI_AST PIL_AST
56 #define IPI_RENDEZVOUS PIL_RENDEZVOUS
57 #define IPI_PREEMPT PIL_PREEMPT
58 #define IPI_STOP PIL_STOP
60 #define IPI_RETRIES 5000
62 struct cpu_start_args {
70 struct tte csa_ttes[PCPU_PAGES];
73 struct ipi_cache_args {
80 struct pmap *ita_pmap;
84 #define ita_va ita_start
88 extern struct pcb stoppcbs[];
90 void cpu_mp_bootstrap(struct pcpu *pc);
91 void cpu_mp_shutdown(void);
93 typedef void cpu_ipi_selected_t(u_int, u_long, u_long, u_long);
94 extern cpu_ipi_selected_t *cpu_ipi_selected;
98 extern struct mtx ipi_mtx;
99 extern struct ipi_cache_args ipi_cache_args;
100 extern struct ipi_tlb_args ipi_tlb_args;
102 extern char *mp_tramp_code;
103 extern u_long mp_tramp_code_len;
104 extern u_long mp_tramp_tlb_slots;
105 extern u_long mp_tramp_func;
107 extern void mp_startup(void);
109 extern char tl_ipi_cheetah_dcache_page_inval[];
110 extern char tl_ipi_spitfire_dcache_page_inval[];
111 extern char tl_ipi_spitfire_icache_page_inval[];
113 extern char tl_ipi_level[];
114 extern char tl_ipi_tlb_context_demap[];
115 extern char tl_ipi_tlb_page_demap[];
116 extern char tl_ipi_tlb_range_demap[];
119 ipi_all_but_self(u_int ipi)
122 cpu_ipi_selected(PCPU_GET(other_cpus), 0, (u_long)tl_ipi_level, ipi);
126 ipi_selected(u_int cpus, u_int ipi)
129 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_level, ipi);
132 #if defined(_MACHINE_PMAP_H_) && defined(_SYS_MUTEX_H_)
134 static __inline void *
135 ipi_dcache_page_inval(void *func, vm_paddr_t pa)
137 struct ipi_cache_args *ica;
141 ica = &ipi_cache_args;
142 mtx_lock_spin(&ipi_mtx);
143 ica->ica_mask = all_cpus;
145 cpu_ipi_selected(PCPU_GET(other_cpus), 0, (u_long)func, (u_long)ica);
146 return (&ica->ica_mask);
149 static __inline void *
150 ipi_icache_page_inval(void *func, vm_paddr_t pa)
152 struct ipi_cache_args *ica;
156 ica = &ipi_cache_args;
157 mtx_lock_spin(&ipi_mtx);
158 ica->ica_mask = all_cpus;
160 cpu_ipi_selected(PCPU_GET(other_cpus), 0, (u_long)func, (u_long)ica);
161 return (&ica->ica_mask);
164 static __inline void *
165 ipi_tlb_context_demap(struct pmap *pm)
167 struct ipi_tlb_args *ita;
172 if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
175 mtx_lock_spin(&ipi_mtx);
176 ita->ita_mask = cpus | PCPU_GET(cpumask);
178 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_context_demap,
180 return (&ita->ita_mask);
183 static __inline void *
184 ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
186 struct ipi_tlb_args *ita;
191 if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
194 mtx_lock_spin(&ipi_mtx);
195 ita->ita_mask = cpus | PCPU_GET(cpumask);
198 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_page_demap, (u_long)ita);
199 return (&ita->ita_mask);
202 static __inline void *
203 ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
205 struct ipi_tlb_args *ita;
210 if ((cpus = (pm->pm_active & PCPU_GET(other_cpus))) == 0)
213 mtx_lock_spin(&ipi_mtx);
214 ita->ita_mask = cpus | PCPU_GET(cpumask);
216 ita->ita_start = start;
218 cpu_ipi_selected(cpus, 0, (u_long)tl_ipi_tlb_range_demap, (u_long)ita);
219 return (&ita->ita_mask);
223 ipi_wait(void *cookie)
225 volatile u_int *mask;
227 if ((mask = cookie) != NULL) {
228 atomic_clear_int(mask, PCPU_GET(cpumask));
231 mtx_unlock_spin(&ipi_mtx);
235 #endif /* _MACHINE_PMAP_H_ && _SYS_MUTEX_H_ */
243 static __inline void *
244 ipi_dcache_page_inval(void *func, vm_paddr_t pa)
250 static __inline void *
251 ipi_icache_page_inval(void *func, vm_paddr_t pa)
257 static __inline void *
258 ipi_tlb_context_demap(struct pmap *pm)
264 static __inline void *
265 ipi_tlb_page_demap(struct pmap *pm, vm_offset_t va)
271 static __inline void *
272 ipi_tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end)
279 ipi_wait(void *cookie)
285 tl_ipi_cheetah_dcache_page_inval(void)
291 tl_ipi_spitfire_dcache_page_inval(void)
297 tl_ipi_spitfire_icache_page_inval(void)
306 #endif /* !_MACHINE_SMP_H_ */