2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2001 Jake Burkholder.
5 * Copyright (c) 2008, 2010 Marius Strobl <marius@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef _MACHINE_TLB_H_
33 #define _MACHINE_TLB_H_
35 #define TLB_DIRECT_ADDRESS_BITS (43)
36 #define TLB_DIRECT_PAGE_BITS (PAGE_SHIFT_4M)
38 #define TLB_DIRECT_ADDRESS_MASK ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1)
39 #define TLB_DIRECT_PAGE_MASK ((1UL << TLB_DIRECT_PAGE_BITS) - 1)
41 #define TLB_PHYS_TO_DIRECT(pa) \
42 ((pa) | VM_MIN_DIRECT_ADDRESS)
43 #define TLB_DIRECT_TO_PHYS(va) \
44 ((va) & TLB_DIRECT_ADDRESS_MASK)
45 #define TLB_DIRECT_TO_TTE_MASK \
46 (TD_V | TD_4M | (TLB_DIRECT_ADDRESS_MASK - TLB_DIRECT_PAGE_MASK))
48 #define TLB_DAR_SLOT_SHIFT (3)
49 #define TLB_DAR_TLB_SHIFT (16)
50 #define TLB_DAR_SLOT(tlb, slot) \
51 ((tlb) << TLB_DAR_TLB_SHIFT | (slot) << TLB_DAR_SLOT_SHIFT)
52 #define TLB_DAR_T16 (0) /* US-III{,i,+}, IV{,+} */
53 #define TLB_DAR_T32 (0) /* US-I, II{,e,i} */
54 #define TLB_DAR_DT512_0 (2) /* US-III{,i,+}, IV{,+} */
55 #define TLB_DAR_DT512_1 (3) /* US-III{,i,+}, IV{,+} */
56 #define TLB_DAR_IT128 (2) /* US-III{,i,+}, IV */
57 #define TLB_DAR_IT512 (2) /* US-IV+ */
58 #define TLB_DAR_FTLB (0) /* SPARC64 V, VI, VII, VIIIfx */
59 #define TLB_DAR_STLB (2) /* SPARC64 V, VI, VII, VIIIfx */
61 #define TAR_VPN_SHIFT (13)
62 #define TAR_CTX_MASK ((1 << TAR_VPN_SHIFT) - 1)
64 #define TLB_TAR_VA(va) ((va) & ~TAR_CTX_MASK)
65 #define TLB_TAR_CTX(ctx) ((ctx) & TAR_CTX_MASK)
67 #define TLB_CXR_CTX_BITS (13)
68 #define TLB_CXR_CTX_MASK \
69 (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT)
70 #define TLB_CXR_CTX_SHIFT (0)
71 #define TLB_CXR_PGSZ_BITS (3)
72 #define TLB_CXR_PGSZ_MASK (~TLB_CXR_CTX_MASK)
73 #define TLB_PCXR_N_IPGSZ0_SHIFT (53) /* SPARC64 VI, VII, VIIIfx */
74 #define TLB_PCXR_N_IPGSZ1_SHIFT (50) /* SPARC64 VI, VII, VIIIfx */
75 #define TLB_PCXR_N_PGSZ0_SHIFT (61)
76 #define TLB_PCXR_N_PGSZ1_SHIFT (58)
77 #define TLB_PCXR_N_PGSZ_I_SHIFT (55) /* US-IV+ */
78 #define TLB_PCXR_P_IPGSZ0_SHIFT (24) /* SPARC64 VI, VII, VIIIfx */
79 #define TLB_PCXR_P_IPGSZ1_SHIFT (27) /* SPARC64 VI, VII, VIIIfx */
80 #define TLB_PCXR_P_PGSZ0_SHIFT (16)
81 #define TLB_PCXR_P_PGSZ1_SHIFT (19)
83 * Note that the US-IV+ documentation appears to have TLB_PCXR_P_PGSZ_I_SHIFT
84 * and TLB_PCXR_P_PGSZ0_SHIFT erroneously inverted.
86 #define TLB_PCXR_P_PGSZ_I_SHIFT (22) /* US-IV+ */
87 #define TLB_SCXR_S_PGSZ1_SHIFT (19)
88 #define TLB_SCXR_S_PGSZ0_SHIFT (16)
90 #define TLB_TAE_PGSZ_BITS (3)
91 #define TLB_TAE_PGSZ0_MASK \
92 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT)
93 #define TLB_TAE_PGSZ1_MASK \
94 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT)
95 #define TLB_TAE_PGSZ0_SHIFT (16)
96 #define TLB_TAE_PGSZ1_SHIFT (19)
98 #define TLB_DEMAP_ID_SHIFT (4)
99 #define TLB_DEMAP_ID_PRIMARY (0)
100 #define TLB_DEMAP_ID_SECONDARY (1)
101 #define TLB_DEMAP_ID_NUCLEUS (2)
103 #define TLB_DEMAP_TYPE_SHIFT (6)
104 #define TLB_DEMAP_TYPE_PAGE (0)
105 #define TLB_DEMAP_TYPE_CONTEXT (1)
106 #define TLB_DEMAP_TYPE_ALL (2) /* US-III and beyond only */
108 #define TLB_DEMAP_VA(va) ((va) & ~PAGE_MASK)
109 #define TLB_DEMAP_ID(id) ((id) << TLB_DEMAP_ID_SHIFT)
110 #define TLB_DEMAP_TYPE(type) ((type) << TLB_DEMAP_TYPE_SHIFT)
112 #define TLB_DEMAP_PAGE (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_PAGE))
113 #define TLB_DEMAP_CONTEXT (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_CONTEXT))
114 #define TLB_DEMAP_ALL (TLB_DEMAP_TYPE(TLB_DEMAP_TYPE_ALL))
116 #define TLB_DEMAP_PRIMARY (TLB_DEMAP_ID(TLB_DEMAP_ID_PRIMARY))
117 #define TLB_DEMAP_SECONDARY (TLB_DEMAP_ID(TLB_DEMAP_ID_SECONDARY))
118 #define TLB_DEMAP_NUCLEUS (TLB_DEMAP_ID(TLB_DEMAP_ID_NUCLEUS))
120 #define TLB_CTX_KERNEL (0)
121 #define TLB_CTX_USER_MIN (1)
122 #define TLB_CTX_USER_MAX (8192)
124 #define MMU_SFSR_ASI_SHIFT (16)
125 #define MMU_SFSR_FT_SHIFT (7)
126 #define MMU_SFSR_E_SHIFT (6)
127 #define MMU_SFSR_CT_SHIFT (4)
128 #define MMU_SFSR_PR_SHIFT (3)
129 #define MMU_SFSR_W_SHIFT (2)
130 #define MMU_SFSR_OW_SHIFT (1)
131 #define MMU_SFSR_FV_SHIFT (0)
133 #define MMU_SFSR_ASI_SIZE (8)
134 #define MMU_SFSR_FT_SIZE (6)
135 #define MMU_SFSR_CT_SIZE (2)
137 #define MMU_SFSR_GET_ASI(sfsr) \
138 (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
139 #define MMU_SFSR_GET_FT(sfsr) \
140 (((sfsr) >> MMU_SFSR_FT_SHIFT) & ((1UL << MMU_SFSR_FT_SIZE) - 1))
141 #define MMU_SFSR_GET_CT(sfsr) \
142 (((sfsr) >> MMU_SFSR_CT_SHIFT) & ((1UL << MMU_SFSR_CT_SIZE) - 1))
144 #define MMU_SFSR_E (1UL << MMU_SFSR_E_SHIFT)
145 #define MMU_SFSR_PR (1UL << MMU_SFSR_PR_SHIFT)
146 #define MMU_SFSR_W (1UL << MMU_SFSR_W_SHIFT)
147 #define MMU_SFSR_OW (1UL << MMU_SFSR_OW_SHIFT)
148 #define MMU_SFSR_FV (1UL << MMU_SFSR_FV_SHIFT)
150 typedef void tlb_flush_nonlocked_t(void);
151 typedef void tlb_flush_user_t(void);
156 extern int dtlb_slots;
157 extern int itlb_slots;
158 extern int kernel_tlb_slots;
159 extern struct tlb_entry *kernel_tlbs;
161 void tlb_context_demap(struct pmap *pm);
162 void tlb_page_demap(struct pmap *pm, vm_offset_t va);
163 void tlb_range_demap(struct pmap *pm, vm_offset_t start, vm_offset_t end);
165 tlb_flush_nonlocked_t cheetah_tlb_flush_nonlocked;
166 tlb_flush_user_t cheetah_tlb_flush_user;
168 tlb_flush_nonlocked_t spitfire_tlb_flush_nonlocked;
169 tlb_flush_user_t spitfire_tlb_flush_user;
171 tlb_flush_nonlocked_t zeus_tlb_flush_nonlocked;
172 tlb_flush_user_t zeus_tlb_flush_user;
174 extern tlb_flush_nonlocked_t *tlb_flush_nonlocked;
175 extern tlb_flush_user_t *tlb_flush_user;
177 #endif /* !_MACHINE_TLB_H_ */